Patents Represented by Attorney IP & T Group LLP

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  • Nonvolatile memory device and method of operating the same
    Patent number: 8270221
    Abstract: A nonvolatile memory device includes a cell string, including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, and memory cells coupled in series between the drain select transistor and the source select transistor, a latch unit, including a first latch for storing a detection result of a threshold voltage of a second memory cell adjacent to a first memory cell selected from among the memory cells and a second latch for storing a detection result of a threshold voltage of the first memory cell, and a first reset unit electrically coupled between the first and second latches and configured to reset the second latch, during a time in which a read operation is performed on the first memory cell, in response to a first reset signal and the detection result stored in the first latch.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: September 18, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ju Yeab Lee
  • Semiconductor memory device and method of reading the same
    Patent number: 8264883
    Abstract: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: September 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyu Hee Lim, Seung Ho Chang, Seong Je Park
  • Nonvolatile memory device and method of programming the same
    Patent number: 8264887
    Abstract: A nonvolatile memory device includes a memory block including a number of cell strings, a channel voltage detection unit configured to detect channel voltages of the cell strings in which the channel voltages are changed based on voltages supplied to memory cells of the cell strings during a program operation and to generate channel voltage code based on an average channel voltage of the detected channel voltages, and a voltage supply unit configured to change a level of a pass voltage of the voltages supplied to memory cells in which the pass voltage is supplied to the memory cells during the program operation according to the channel voltage code.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: September 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: In Suk Yun, Kee Han Rho
  • Semiconductor memory device and driving method thereof
    Patent number: 8259529
    Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Myoung-Jin Lee, Jin-Hong An
  • Transmission and method of shift control for transmission
    Patent number: 8256312
    Abstract: A transmission includes a controller that has a rapid-deceleration judge and a rapid-deceleration processor. The rapid-deceleration judge judges whether a vehicle is decelerating rapidly or not. The rapid-deceleration processor includes a torque-fluctuation inhibitor, and an after-rapid-deceleration change-speed stage anticipator. The torque-fluctuation inhibitor shuts off power transmission from a power source, or holds power transmission by way of a current change-speed stage or lower, when the vehicle is decelerating rapidly. The after-rapid-deceleration change-speed stage anticipator anticipates a subsequent change-speed stage being adapted for restarting or reaccelerating the vehicle that has come out of rapid deceleration.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: September 4, 2012
    Assignees: Aisin AI Co., Ltd., Aisin AW Co., Ltd.
    Inventors: Hiroki Hatori, Takeshige Miyazaki, Yoshiki Ito, Hiroshi Toyoda, Kiyoshi Nagami, Atsushi Takeuchi
  • Delay locked loop for expanding a delay range
    Patent number: 8258838
    Abstract: A delay locked loop includes a delay amount setting unit configured to set a delay amount of an external clock signal, a coarse delay unit configured to primarily delay the external clock signal by the set delay amount based on a first unit duration which is a unit delay amount of the coarse delay unit; and a fine delay unit configured to secondarily finely delay the primarily delayed clock signal based on a second unit duration, which is a unit delay amount of the fine delay unit and smaller than the first unit duration.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seon-Kwang Jeon
  • Synchronous semiconductor memory device
    Patent number: 8259519
    Abstract: A synchronous semiconductor memory device includes a data alignment reference pulse generation unit configured to generate a data alignment reference pulse in response to a data strobe signal, a data alignment suspension signal generation unit configured to generate a data alignment suspension signal in response to the data alignment reference pulse, a data strobe termination signal, and a write pulse, and a data alignment unit configured to align input data in response to the data alignment reference pulse and stop aligning the input data in response to the data alignment suspension signal.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang-Youl Lee
  • Delay locked loop and integrated circuit including the same
    Patent number: 8258840
    Abstract: A delay locked loop includes a first delay unit configured to output an output clock by delaying an input clock by a delay; a replica delay unit configured to output a feedback clock by delaying the output clock with a delay equal to a sum of a first delay amount for a first operational frequency of the delayed locked loop and an additional delay amount for a second operational frequency of the delayed locked loop, wherein the second operational frequency is lower than the first operational frequency; and a delay amount control unit configured to control the delay of the first delay unit by comparing a phase of the input clock with a phase of the feedback clock.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Sic Yoon
  • Semiconductor device and method for operating the same
    Patent number: 8258843
    Abstract: A semiconductor device includes a clock delay section configured to receive an external clock signal, reflect different delay amounts on the external clock signal, and generate a plurality of synchronization clock signals, a clock synchronization section configured to synchronize a clock enable signal with each of the plurality of synchronization clock signals in an order beginning with a synchronization clock signal, on which a largest delay amount is reflected, to a synchronization clock signal, on which a smallest delay amount is reflected, and to generate a synchronized clock enable signal, and an internal clock generation section configured to generate an internal clock signal corresponding to the external clock signal, and to be on/off controlled in its operation in response to the synchronized clock enable signal.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hoon Choi, Kwang-Jin Na
  • Semiconductor memory device and delay locked loop control method thereof
    Patent number: 8254188
    Abstract: A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min-Young You
  • Internal voltage control circuit
    Patent number: 8253480
    Abstract: An internal voltage control circuit includes active drivers, a control unit, and a time interval adjustment unit. The active drivers are configured to receive a common internal voltage. The control unit is configured to control respective enable operations of the active drivers. The time interval adjustment unit is configured to respectively supply enable signals, generated by the control unit, to the active drivers at respective predetermined time intervals.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Sam Kim
  • Addressing circuit of semiconductor memory device and addressing method therefor
    Patent number: 8254203
    Abstract: The addressing circuit of a semiconductor memory device includes a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted data in response to register control signals, and a control unit configured to generate the register control signals, using defect information of respective memory cell arrays, to control whether or not the register units store the inputted.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jin Su Park
  • Signal delay circuit, clock transfer control circuit and semiconductor device having the same
    Patent number: 8248129
    Abstract: A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyoung-Jun Na, Kyung-Whan Kim
  • ESD protection circuit including multi-finger transistor
    Patent number: 8247872
    Abstract: Provided is an electrostatic discharge (ESD) protection circuit including a multi-finger transistor. The multi-finger transistor includes a plurality of drains and a plurality of sources alternately arranged in parallel, and a plurality of gate electrodes arranged between the drains and the sources. The drains are electrically coupled to an input/output pad through a plurality of first finger patterns which are coupled to a plurality of first contact patterns. The sources are electrically coupled to a specific voltage line through a path which comprises a plurality of second finger patterns coupled to a plurality of second contact patterns. The number of the first contact patterns corresponding to the drains is gradually reduced as the distance to the voltage line becomes shorter.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee-Jeong Son
  • Power-up signal generator for use in semiconductor device
    Patent number: 8248882
    Abstract: In an apparatus for generating a power-up signal, a mode register set (MRS) and other circuits are prevented from being reset, thereby providing stable circuit operation. A final power-up signal is not disabled even though an internal voltage generating unit is turned off at a test mode. The apparatus includes a power-up signal generator for producing a power-up signal; a multiplexing unit for selectively outputting the power-up signal or a static voltage signal in a test mode; and a power-up signal generator for producing a final power-up signal in response to the power-up signal of the power-up signal generator and an output signal of the multiplexing unit as the final power-up signal.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sang-Jin Byeon
  • Semiconductor memory device and test method thereof
    Patent number: 8248872
    Abstract: A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy memory cell corresponding to the external address to be accessed in response to the repair control signal and an internal active signal, and an activation interval detection unit configured to generate an interval detection signal by detecting a time interval between an activation timing of the repair control signal and an activation timing of the internal active signal in a test operation mode.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kwi-Dong Kim
  • Semiconductor device with buried gate and method for fabricating the same
    Patent number: 8247324
    Abstract: A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong-Han Shin, Jum-Yong Park
  • Output circuit of semiconductor device
    Patent number: 8248103
    Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang-Kyu Choi, Kyung-Hoon Kim
  • Semiconductor integrated circuit
    Patent number: 8242835
    Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: August 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ho-Don Jung
  • Delay locked loop
    Patent number: 8242822
    Abstract: A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 14, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung-Joon Ahn, Jong-Chern Lee