Abstract: A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.

Abstract: A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory device includes a multi-purpose register configured separately to store a plurality of information, and to control a bit rate of the stored information in a test mode, each of the information having multiple bits, and a connection selector configured selectively to connect an output terminal of the multi-purpose register to one of a number of global lines according to an operation mode.

Abstract: A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit configured to delay a phase of an internal clock synchronized with a clock edge of the source clock in response to an output signal of the phase comparator. The clock delay circuit delays the phase of the internal clock using first delay units for a predetermined delay duration, and thereafter delays the phase of the internal clock using second delay units, the second delay unit providing a longer delay than the first delay unit. A delay replica model is configured to reflect actual delay conditions of the source clock in an output clock of the clock delay circuit to output the feedback clock.

Abstract: A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines, for synchronizing time that the plurality of data transferred through the respective data lines take to arrive at the receiver.

Abstract: An internal voltage generator of a semiconductor memory device generates an internal voltage sensitive to a change in a temperature. The internal voltage generator includes a reference voltage generator, an internal voltage detecting unit and an internal voltage pumping unit. The reference voltage generator generates a reference voltage which is inversely proportional to the change in the temperature. The internal voltage detecting unit detects a difference between the reference voltage and the internal voltage to output a pumping control signal according to a detecting result, wherein the pumping control signal has an identical temperature characteristic as the reference voltage. The internal voltage pumping unit generates the internal voltage by a pumping operation in response to the pumping control signal.

Abstract: A probe-testing device includes probe tips configured to apply inputs to pads of a semiconductor chip, wherein one of the probe tips is connected to a calibration pad for impedance adjustment and a calibration resistor is connected thereto.

Abstract: A semiconductor memory device includes a drive clock supplier and a signal generator. The drive clock supplier supplies a drive clock which is obtained by dividing an internal clock with a divide ratio, wherein the drive clock synchronizes with a rising edge of the internal clock with which an internal write signal synchronizes. The signal generator counts time corresponding to a write-recovery on the basis of the drive clock, to generate a precharge signal.

Abstract: A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

Abstract: A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line.

Abstract: A method for forming a capacitor of a semiconductor device includes forming a first capacitor in a storage node contact region to form a two-stage structured capacitor, thereby increasing the height and the capacitance of the capacitor.

Abstract: A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

Abstract: A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.

Abstract: A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.

Abstract: A semiconductor memory device has a memory cell having a hierarchical bit line structure for large capacity even in a small cell size. The semiconductor memory device comprises a unit cell configured to read/write data, a cell data sensing unit configured to adjust a current amount of a main bit line depending on a sensing voltage of a sub bit line when data are sensed, and a write control unit configured to store data in the corresponding unit cell depending on a current level applied from the main bit line to the sub bit line.

Abstract: A semiconductor memory device includes a command decoder, a refresh address counter, an address delivery unit, and an address output selector. The command decoder decodes a command signal to generate a refresh signal. The refresh address counter generates a refresh address in response to the refresh signal. The address delivery unit delivers one of the refresh address and an address from outside of the semiconductor memory device to a memory core area. The address output selector outputs the refresh address to the outside of the semiconductor memory device.

Abstract: A semiconductor memory device is capable of performing a normal operation, while detecting an internal voltage without a special bonding method during a test mode. The semiconductor memory device comprises a switching unit and an internal reference voltage generating unit. The switching unit transfers one of an internal and an external reference voltages according to whether a test mode is being performed, wherein the external reference voltage is input from outside of the semiconductor memory device. The internal reference voltage generating unit generates the internal reference voltage having the same level of the external reference voltage to thereby supply the internal reference inside the semiconductor memory device during the test mode.

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating pattern over a semiconductor substrate. The interlayer insulating pattern defines a plurality of storage node regions. A lining conductive film is formed over the interlayer insulating pattern including the storage node region. A capping insulating film is formed over the lining conductive film. The capping insulating film over the interlayer insulating film and the lining conductive film are selectively etched between two neighboring storage node regions to form a recess exposing the interlayer insulating pattern on the bottom of the recess and the lining conductive film on sidewalls of the recess. The capping insulating film and the lining conductive film is shaped to be planar so that the lining conductive layer is electrically separated from each other to form a respective lower storage electrode. A supporting pattern is formed to fill the recess.

Abstract: A circuit including a comparing unit for comparing a target voltage with a stepwise-varying tracking voltage, a counting unit for counting a code according to the comparison result of the comparing unit and a control signal generating unit for generating a signal for controlling a counting operation of the counting unit.

Abstract: A synchronous semiconductor memory device including a data alignment reference pulse generating unit configured to generate a data alignment reference pulse in response to a data strobe signal (DQS), an alignment hold signal generating unit configured to generate an alignment hold signal, which is activated during a period corresponding to a postamble of the data strobe signal, in response to the data alignment reference pulse and a data input clock, and a data alignment unit configured to align input data in response to the data alignment reference pulse and the alignment hold signal.

Abstract: Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals.