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  • On-die termination device
    Patent number: 7692446
    Abstract: An on-die termination includes: a code generator configured to generate a calibration code in response to a voltage of a first node and a reference voltage; a calibration resistor unit connected to the first node, and configured to be turned on and off in response to the calibration code; and a reference resistor unit coupled to the calibration resistor unit, and configured to be turned on and off in response to a control signal.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: April 6, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Geun-Il Lee, Chang-Kyu Choi
  • Semiconductor package
    Patent number: 7693003
    Abstract: A semiconductor package facilitates package connection due to different locations of input/output pads in each interlayer die depending on coding information in a multi-chip package. The semiconductor package includes many chips. Each of the chips includes: input/output pads configured to input and output data having a given bandwidth; a decoding pad configured to receive coding information; and a code control unit configured to decode the coding information and to enable an input/output pad positioned at a specific location among the input/output pads according to the decoding result.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: April 6, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Shin Ho Chu
  • Semiconductor memory device and method for operating the same
    Patent number: 7688124
    Abstract: A semiconductor memory device has a DLL circuit capable of suppressing EMI without distorting a DLL clock required in high-speed operation. The semiconductor memory device includes a delay locked loop (DLL) circuit configured to be responsive to a system clock to output a DLL clock having a phase that is changed when electromagnetic interference (EMI) is detected, for the DLL clock to have frequencies within a delay locking range, and a data output circuit configured to output data in synchronization with the DLL clock.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Hoon Choi
  • Multi-port memory device having serial input/output interface
    Patent number: 7687924
    Abstract: A multi-port memory device includes a first package ball out region in which a plurality of balls for a serial I/O interface part are arranged; and a second package ball out region in which a plurality of balls for a dynamic random access memory (DRAM) part are arranged.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jae-Hyuk Im, Chang-Ho Do
  • Method for fabricating semiconductor device
    Patent number: 7687389
    Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a first gate conductive layer over the gate insulation layer, forming a barrier metal over the first gate conductive layer, sequentially forming a second gate conductive layer and a gate hard mask over the barrier metal, patterning the gate hard mask, the second gate conductive layer, the barrier metal, the first gate conductive layer, and the gate insulation layer to form a gate pattern, and performing a plasma selective gate re-oxidation process on the gate pattern.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kwan-Yong Lim, Min-Gyu Sung, Heung-Jae Cho, Hong-Seon Yang
  • Semiconductor memory device with high voltage generator
    Patent number: 7688647
    Abstract: A semiconductor memory device which prevents a drop of the level of an external voltage due to generation of high voltage, thereby ensuring an effective data window. The semiconductor memory device includes a level detecting unit and a voltage generating unit. The level detecting unit is configured to detect a level of an internal voltage based on a reference voltage to output a level detection signal. The voltage generating unit is configured to generate the internal voltage by selectively pumping an external voltage according to the level detection signal and a refresh signal.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Ho-Don Jung
  • Calibration circuit of on-die termination device
    Patent number: 7683657
    Abstract: A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node and a reference voltage, to generate calibration codes. The calibration unit also includes a calibration resistor unit having parallel resistors which are turned on/off in response to each of the calibration codes and connected to the calibration node, a turn-on strength of at least one of the parallel resistors being controlled by a control signal.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: March 23, 2010
    Assignee: Hybix Semiconductor, Inc.
    Inventor: Ki-Ho Kim
  • Flash memory device and method for driving the same
    Patent number: 7684260
    Abstract: A flash memory device includes a data input/output pad and a core region in which a plurality of unit cells are arranged. A data input buffer is configured to receive command and address data through the data input/output pad and transfer the received command and address to the core region. A data output buffer is configured to output the data through the data input/output pad, and a data input controller is configured to detect an outputting of the data and disable the data input buffer.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Bok-Rim Ko
  • High integrated open bit line structure semiconductor memory device with precharge units to reduce interference or noise
    Patent number: 7684271
    Abstract: A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Hyung-Sik Won
  • Semiconductor memory device
    Patent number: 7684269
    Abstract: A semiconductor memory device is capable of measuring internal voltages via a shared pad to reduce a chip size. The semiconductor memory device includes a selector and a monitoring pad. The selector is configured to select one of a plurality of internal signals in response to a test signal and output the selected internal signal. The monitoring pad is configured to output an output signal of the selector to an outside of the semiconductor memory device.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Khil-Ohk Kang
  • Semiconductor memory device
    Patent number: 7684268
    Abstract: A semiconductor memory device includes: a plurality of cell array blocks; a boosted voltage driving unit for selectively supplying a boosted voltage to the cell array blocks; and a controller controlling a driving operation of the boosted voltage driving unit in response to a cell array block select signal.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: March 23, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Sang-Il Park, Saeng-Hwan Kim
  • Method for fabricating semiconductor device with recess gate
    Patent number: 7678676
    Abstract: A method for fabricating a semiconductor device with a recess gate includes providing a substrate, forming an isolation layer over the substrate to define an active region, forming mask patterns with a first width opening exposing a region where recess patterns are to be formed, and a second width opening smaller than the first width and exposing the isolation layer, forming a passivation layer along a height difference of the mask patterns, etching the substrate using the passivation layer and the mask patterns as an etch barrier to form recess patterns, removing the passivation layer and the mask patterns, and forming gate patterns protruding from the substrate to fill the recess patterns.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: March 16, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Hae-Jung Lee, Jae-Seon Yu, Jae-Kyun Lee, Sang-Rok Oh
  • Test circuit for testing command signal at package level in semiconductor device
    Patent number: 7676711
    Abstract: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: March 9, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Hong-Sok Choi
  • Semiconductor memory device
    Patent number: 7675810
    Abstract: An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: March 9, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jee-Yul Kim, Beom-Ju Shin
  • Delay locked loop circuit and synchronous memory device including the same
    Patent number: 7676686
    Abstract: A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) enables a more stable operation when the semiconductor operates in a power-down mode for low power. The present invention can prevent a phase update operation from being interrupted when the DLL circuit enters a power-down mode. For the above purpose, an off operation of a clock buffer is delayed until a clock signal notifying a final period of the phase update is activated.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: March 9, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Young-Jun Ku, Ji-Eun Jang
  • Power-up signal generating circuit and method for driving the same
    Patent number: 7675331
    Abstract: A power-up signal generating circuit that prevents repeatedly generating a power-up signal even when there is noise on an external voltage. The power-up signal generating circuit includes a level detector, a level comparator, and a reentry protector. The level detector is configured to deactivate a first level detection signal when a level of an external voltage increases above a upper limit reference voltage. The level comparator is configured to deactivate a second level detection signal when the level of the external voltage increases above a lower limit reference voltage. The reentry protector is configured to activate the power-up signal in response to the second level detection signal and deactivate the power-up signal in response to a deactivation of the first level detection signal.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 9, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Ho-Don Jung
  • Equalizing circuit for semiconductor memory device
    Patent number: 7672174
    Abstract: A semiconductor memory device includes an equalizing signal generation circuit comprising a clamping circuit that clamps a voltage level less than the voltage level of a high voltage level by being controlled by the high voltage, and an equalizing signal driver receiving an output signal of the equalizing signal generation circuit as a driving signal.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Kang-Seol Lee
  • Data output control circuit
    Patent number: 7672191
    Abstract: A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit 0 when the DLL circuit 0 is disabled, without compensating the delay amount.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Ji-Eun Jang
  • Apparatus and method for generating multi-phase clocks
    Patent number: 7671649
    Abstract: An apparatus for generating multi-phase clocks in accordance with the present invention includes a clock delay configured to delay a source clock by a delay time corresponding to a control signal to generate a plurality of clocks; a clock multiplexer configured to output a first clock for a first locking region and a second clock for a second locking region sequentially as a selected clock in response to a locking detection signal; a phase detector configured to detect a phase of the selected clock in comparison to a phase of the source clock to output a phase detection signal; and a control voltage signal generator configured to generate the control signal corresponding to the phase detection signal.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Kwang-Jin Na
  • Semiconductor memory device with two-stage input buffer
    Patent number: 7672183
    Abstract: A semiconductor memory device includes: a pre-amplifying unit configured to amplify a difference between an input signal and a reference signal to output a pre-output signal; a delaying unit configured to delay the input signal to output a delayed input signal; and a main amplifying unit configured to receive the pre-output signal and the delayed input signal as differential inputs to output an output signal.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Yong-Suk Joo, Byoung-Jin Choi