Abstract: A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.

Abstract: A duty cycle correction circuit and a delay locked loop circuit including the same are capable of reducing area and power consumption of a circuit. The delay locked loop circuit includes a delay locked loop unit, a delay controller, a duty cycle ratio correction circuit, and a duty cycle ratio detector. The delay locked loop unit outputs an internal clock by delaying an external clock in order to compensate a clock skew. The delay controller outputs a delay internal clock by delaying the internal clock in response to correction signals. The duty cycle ratio correction circuit outputs an internal correction clock by increasing or decreasing a high level section of the internal clock according to the correction signals. The duty cycle ratio detector outputs the correction signals in accordance with a duty cycle ratio of the internal correction clock.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of memory cells connected serially between a bit line and a sensing line, a first switching unit configured to selectively connect the memory cells to the bit line in response to a first selecting signal, and a second switching unit configured to selectively connect the memory cells to the sensing line in response to a second selecting signal. The first switching unit and the second switching unit have the same structure as that of the memory cell.

Abstract: A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.

Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.

Abstract: An impedance matching circuit of a semiconductor memory device performs a ZQ calibration with initial values that reflect an offset error according to variations in a manufacturing process. The impedance matching circuit includes a first pull-down resistance unit, a first pull-up resistance unit, and a code generation unit. The first pull-down resistance unit supplies a ground voltage to a first node, thereby determining an initial pull-down code. The first pull-up resistance unit supplies a supply voltage to the first node, thereby determining an initial pull-up code or a voltage level on the first node. The code generation unit generates pull-down and pull-up calibration codes using the initial pull-down and pull-up codes as respective initial values.

Abstract: A semiconductor memory device stably performs a write operation with reduced current consumption. The semiconductor memory device includes a global data, a control unit, a termination resistor unit, and a storage unit. The global data line transmits data. The control unit generates a global control signal during a read operation or a write operation. The termination resistance unit supplies termination resistance to the global data line in response to the global control signal. The storage unit stores the data transmitted to the global data line while the termination resistance unit is inactivated. A method for driving the semiconductor memory device includes detecting a read operation or a write operation and supplying termination resistance when the read or write operation is detected.

Abstract: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection unit and a selection signal corresponding to a data operation mode; an oscillator for generating clock signals having different frequencies in response to the first control signal and the second control signal; and a pumping unit for generating the high voltage by performing a charge pumping operation in response to the clock signals.

Abstract: A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal.

Abstract: A semiconductor memory device that includes a first high voltage oscillator configured to generate a first control pulse in response to a first enable signal, a level shifter configured to generate a high voltage control pulse by boosting a level of the first control pulse using a source high voltage, and a first high voltage generator configured to generate a high voltage by boosting an external power supply voltage in response to the high voltage control pulse.

Abstract: A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.

Abstract: A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock signal; an internal command signal generator for generating an internal command signal in response to an external command; a delay circuit for delaying the internal command signal by a delay time corresponding to a delay time of the DLL to output a delayed internal command signal; and an output enable signal generator for generating an output enable signal based on the delayed internal command signal and the DLL clock signal.

Abstract: An internal voltage generation device includes a plurality of output nodes; a bit line precharge voltage generation unit for generating a bit line precharge voltage; a first voltage drop unit for transferring the bit line precharge voltage to a first output node after decreasing the bit line precharge voltage by a first voltage drop amount in response to a test mode signal; and a second voltage drop unit for transferring the bit line precharge voltage to a second output node after decreasing the bit line precharge voltage by a second voltage drop amount in response to the test mode signal, wherein the second voltage drop amount is greater than the first voltage drop amount.

Abstract: A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal.

Abstract: A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.

Abstract: A one-transistor type DRAM comprises a floating body storage element configured to store data in a floating body in a SOI wafer, a plurality of access transistors each connected between a bit line and one end of the floating body storage element, a word line configured to control the floating body storage element, and a plurality of port word lines each configured to select one of the plurality of access transistors.

Abstract: Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent upon a temperature variation, a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal, and a self refresh signal generating unit for receiving a self refresh entry signal and generating a self refresh signal of temperature compensated cycle under the control of the comparison result signal.

Abstract: A semiconductor memory device changes a pulse width of an over driving signal according to operation modes, which differ by a degree of accessing memory banks during an over driving operation. An over driver supplies an RTO line of the bit line sense amplifier with an over driving voltage in response to the over driving signal and an over driving signal generator changes a pulse width of the over driving signal according to the operation modes. An increase in the VCORE due to excess supply voltage VDD in the over driving operation is prevented.

Abstract: A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses to an internal circuit and store one or more of the received normal addresses. The second address buffer unit is configured to transmit one or more external bank addresses to the internal circuit as internal bank addresses in a normal mode and transmit addresses stored in the first address buffer unit to the internal circuit as the internal bank addresses in a test mode.

Abstract: A semiconductor memory device is capable of performing a modulation of output clock signals in order to prevent EMI characteristics of a system having the semiconductor memory device from being degraded. The semiconductor memory device includes a modulation clock signal generator, a clock input unit, a first modulation unit, a delay locked loop circuit, and a second modulation unit. The modulation clock signal generator generates a modulation clock signal. The clock input unit generates a reference clock signal from a system clock signal. The first modulation unit generates a modulated clock signal by modulating the reference clock signal with the modulation clock signal. The delay locked loop circuit performs a delay locking operation on the modulated clock signal to generate a delay locked clock signal. The second modulation unit modulates the delayed locked clock signal with the modulation clock signal.