Abstract: One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input.

Abstract: An over-current condition is detected in a synchronous DC-DC converter by sampling and holding a measured load current value. The load current is sampled while a low-side transistor is ON and then held when the low-side transistor is OFF. The held value is compared to a threshold value while the low-side transistor is OFF. The comparison occurs during the portion of the cycle when the low-side transistor is OFF so that a comparator has sufficient time in which to detect the over-current condition, even in high duty cycle applications.

Abstract: A method is provided for driving a plurality of light emitters in a plurality of output paths with each output path including at least one light emitter. The method includes the steps of applying a supply voltage level to a plurality of output paths; generating a current for each path during a period of a predetermined length for the output path; sensing a current level for each output path during the period; comparing each sensed current level with a reference level; increasing the supply voltage level if the sensed current level is lower than the reference level; determining a lowest supply voltage level for the worst case output path; and using the lower supply voltage level as a common supply voltage level for all output paths.

Abstract: An active RC filter (20) includes a first resistive element (23) and a first capacitor array (10/50) which co-acts with the first resistive element (23) to determine a bandwidth characteristic of the programmable active RC filter circuit (20). The total filter capacitance is programmed by switching various first capacitors (4-0, 1, 2 . . . 7) of a first capacitor array (10) in parallel between first and second terminals of the first capacitor array in response to a control word (B0, 1, 2 . . . 7) to determine a first portion of the bandwidth characteristic, and by switching various second capacitors (7-0, 1, 2 . . . 6) of the first capacitor array between the first and second terminals of the first capacitor array in parallel with various ones of the first capacitors (4-0, 1, 2 . . . 7) of the first capacitor array (10) in response to less significant bits (B0, 1, 2 . . . 6) of the control word (B0, 1, 2 . . . 7) to determine a second portion of the bandwidth characteristic.

Abstract: An integrated electronic device includes circuitry for providing a regulated output supply voltage level at an output node from an adjustable current. The circuitry includes an adjustable current source for providing the adjustable current and for adjusting the adjustable current to a magnitude of a target value in response to a configuration signal, an auxiliary adjustable current source providing an auxiliary adjustable current having a magnitude corresponding to the target value, and an output supply voltage level regulating loop coupled to the output node and adapted to keep the output supply voltage level at a preset value. A current selecting stage is adapted to receive the adjustable current and the auxiliary current. The current selecting stage is further adapted to supply a selected current corresponding to a lesser value of the adjustable current and the auxiliary adjustable current.

Abstract: An LED controller is provided that can easily control light-on testing of LEDs. A super voltage can be added to a signal including a low voltage and a high voltage. When the super voltage is not detected, LED driving circuit is operated in normal mode. When the super voltage is detected, LED driving circuit is operated in test mode. In test mode, the LEDs are turned on by a test signal directly input to LED driving circuit instead of by light emission data sent from shifter register to storage circuit. Accordingly, light-on testing of LEDs can be carried out easily.

Abstract: Digital predistortion system, methods and circuitry for adapting a predistortion system linearizing a non-linear element. The system is a multiply partitioned architecture that addresses long or “memory” effects, and separately addresses shorter duration effects. In a preferred method, the non-linear element is first modeled in software as a nonlinearity and a linearity in cascade form, preferably a Wiener model. The model is validated and adapted to minimize an observed error between the model and the non-linear element. The software model of the non-linear element is then used first to model a predistortion block that addresses short duration effects, and second to separately model a predistortion block that addresses longer duration effects. The models are software executable by an external processor in real time. Periodically the models are executed and used to update the adaptive parameters of the predistortion system without interrupting the system operation.

Abstract: Various apparatuses, methods and systems for a real time clock are disclosed herein. For example, some embodiments provide a real time clock including a clock generator having a first input connected to a clock signal and a second input connected to a time set signal. The clock generator produces a time change signal at an output of the clock generator. Counters, each adapted to track a different unit of time, are connected to the time change signal. The clock generator is adapted to generate a pulse on the time change signal for each pulse of the time set signal, and to generate separate pulses on the time change signal for consecutive pulses on the clock signal and the time set signal.

Abstract: Programmable power distribution switches with two-level current sensing are disclosed. In a particular example, a power distribution switch includes a programmable output device having a resistance based on a programmed maximum output current and generates an output voltage based on the resistance and a load current. The example power distribution switch also includes a reference voltage generator that is configured to generate a reference voltage corresponding to the output voltage when the load current is substantially equal to the programmed maximum output current. A current limiter is also included to reduce the load current in response to a comparison of the output voltage and the reference voltage, when the comparison is indicative of the load current exceeding the programmed maximum output current.

Abstract: Conventional drivers for transducers oftentimes did not provide an efficient driving mechanism because the driving signal was not “close enough” to the natural frequency of the transducer. Here, a driver for a transducer is provided that measures the natural frequency of the transducer and generates a driving signal accordingly. Thus, a more efficient driver is provided.

Abstract: The accelerator output stage circuit includes: a high side output device coupled to an output node; a low side output device coupled to the output node; a first logic gate coupled to a control node of the first high side output device; a second logic gate coupled to a control node of the second high side output device; a high side one-shot device having an output coupled to a first input of the first logic gate; a low side one-shot device having an output coupled to a first input of the second logic gate; and a feedback device coupled between the output node and a second input of the first logic gate, and between the output node and a second input of the second logic gate, and between the output node and the input to the high side resistor bypass device, and between the output node and the input to the low side one-shot resistor bypass device.

Abstract: An electronic device includes circuitry for driving a light-emitting diode (LED) or other light-emitting semiconductor device.

Abstract: A synchronous buck converter operates in a PWM mode of operation and switches to light-load mode of operation under a light-load condition. When operating in the light-load mode, the synchronous buck converter transitions between a burst mode and an idle mode of operation. In the burst mode of operation, the converter operates with a fixed but increased duty ratio, with respect to the PWM mode of operation, that installs additional energy in an output capacitor. In the idle mode of operation, the high-side and low-side transistors are each turned off. To maximize energy savings and to quickly transition back to the PWM mode of operation if the load increases, a limit as to the number of allowed switching cycles when bursting is imposed and a minimum ratio of the number of clock cycles when idling to the number of switching cycles when bursting is set. Additionally, a comparator is provided to detect a sudden step-increase in the load to quickly switch the converter back to the PWM mode of operation.

Abstract: A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the watchdog circuit can provide adjustments to the DLL so as to change the length of the delay of the delay line to bring it within a predetermined range.

Abstract: A semiconductor device includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: An apparatus is provided. The apparatus comprises a reference circuit and a startup circuit. The reference circuit is adapted to provide a startup current, while the startup circuit receives the startup current and outputs an output voltage. The startup circuit includes a current mirror, a first NMOS transistor, a second NMOS transistor, diodes, and a third NMOS transistor, and a control circuit. The first and second NMOS transistors are coupled to the current mirror at their sources and are coupled to one another and to the reference circuit at their gates. The diodes are coupled between the gate of the second NMOS transistor and the source of the second NMOS transistor, and the third NMOS transistor is coupled to the source of the second NMOS transistor at its gate (which also provides the output voltage at its source). The control circuit is then coupled to the drains of the first and second NMOS transistors.

Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

Abstract: A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or ?'s of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor.

Abstract: A system for measuring a capacitor (CSENj) precharges a CDAC (23) in a SAR converter (17) to a reference voltage (VAZ) and also precharges a first terminal (3-j) of the capacitor to another reference voltage (GND). During a measurement phase, the CDAC is coupled between an output and an input of an amplifier (31) and the capacitor also is coupled to the input of the amplifier, so as to redistribute charge between the capacitor and the CDAC. The amplifier generates an output voltage (VAMP) representing the capacitance being measured. The output voltage is stored in the CDAC. The SAR converter converts the output voltage to a digital value representing the capacitance being measured.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.