Abstract: A digital audio system including a combination of analog and digital volume control is disclosed. A variable power supply voltage biases a power amplifier for each channel, and applies a bias voltage corresponding to an analog volume control signal. In one disclosed embodiment, digital gain control circuitry compares the bias voltage with the level expected for the analog volume control signal; if the bias voltage has not dropped in response to a reduction in the analog volume control signal, the digital gain control circuitry reduces the digital gain of the input digital audio signal, until the bias voltage responds to the reduced volume. In another disclosed embodiment, modeling or characterization of the audio system is used to derive a digital gain control signal based on the desired volume signal and the amplitude of the digital audio signal itself.

Abstract: Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input stage and output stage along with a control loop. Collectively, these components operate together to drive the LED with a low headroom voltage while still achieving high driver performance in terms of edge speed and jitter.

Abstract: The objective of this invention is to provide a boost circuit that reduces power consumption and prevents malfunctioning when the input voltage becomes greater than a target voltage for the output voltage. Control circuit module 5 sets both control signals HCNT2 and LCNT2 to low level “L” when the conditions “output voltage VBoost is higher than voltage OVREF” and “voltage (VIN+VOFFSET) is higher than output voltage VBoost” are satisfied. With this, in boost circuit module 7, switch SWH will be off and switch SWL will be on to forcibly switch to mode B. In mode B, because switch SWH is on, output voltage VBoost will be near input voltage VIN, and the power consumption can be reduced.

Abstract: An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for etching the cavity. An SiO2 pillar (25) extends from a bottom of the cavity to engage and support a portion of the dielectric layer extending over the cavity. In one embodiment, a cap layer (34) on the dielectric layer covers the etchant openings.

Abstract: An apparatus is provided. The apparatus comprises an input circuit, a startup circuit, and a current limiter. The input circuit is coupled to a first source and is adapted to provide a first voltage and a first current to a load having a capacitance. The startup circuit is coupled to the input circuit and to the first source, and the startup circuit includes a current source and a startup capacitor coupled in series with one another. The current limiter has a cascode circuit and a discharge circuit. The cascode circuit has a bias transistor and a power transistor coupled in series with one another to provide a second voltage and a second current to the load, where the bias transistor is coupled to a second source and where the bias transistor generally operates as source follower during startup. The discharge circuit is coupled to a node between the bias transistor and the power transistor of the cascode circuit and coupled to a node between the startup current source.

Abstract: An apparatus is provided. The apparatus comprises a first current source and a second current source that charge and discharge a capacitor. Coupled between the capacitor and the second current source is a switch that can be actuated and deactuated by a controller. Preferably, the controller is coupled to the capacitor and receives a first threshold voltage and a second threshold voltage so that it can actuate the switch if the voltage across the capacitor is greater than the first threshold voltage and deactuate the switch if the voltage across the capacitor is less than the second threshold voltage. Additionally, there is a comparator that is coupled to the capacitor that compares the voltage across the capacitor to a reference voltage, and there is a a multiplexer that is coupled to the capacitor and that is coupled to the comparator.

Abstract: A low-EMI switched circuit comprises two or more switches, wherein impedance transitions of the switches are overlapped and the overlap is varied using variable switch timing based on an output power level of the switched circuit. The variable timing results in a variable impedance overlap between the switches. In one example, when one switch turns off (begins a low to high impedance transition) and a second switch turns on (begins a high to low impedance transition), a greater timing delay in beginning the second switch's transition results in a higher switch impedance overlap than a shorter delay does. If the variable timing is based on output power of the switched circuit, the variable delay can operate to reduce fly-back voltages at high power output levels and reduce shoot-through current at lower power levels, reducing EMI and quiescent current of the switched circuit.

Abstract: A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 MHz.

Abstract: A LED drive circuit equipped with oscillator 18, up/down counter 20, and DAC 22 in order to drive multiple LEDs 10(1)-10(m) in a block. Up/down counter 20 carries out count-up/down operations in sync with clock CLK sent from oscillator 18 during the ramping up/down of pulse-lighting of the LEDs. DAC 22 converts counter count value DN into analog voltage signal VDAC and supplies it to the gate terminal of NMOS transistor 14 via low-pass filter 28 and buffer amplifier 24.

Abstract: With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced.

Abstract: An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements.

Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Abstract: A Universal Serial Bus (USB) switch matrix is provided. The switch matrix generally comprises a switch network, and amplifier, a adjustable current source, and variable resistors. The switch network is able to output a differential output signal and a common mode signal. The amplifier compares the common mode signal to a reference voltage, and the amplifier adjusts the magnitude of the current from the adjustable current source and the resistances of the variable resistors based at least in part on the comparison to adjust the peak-to-peak voltage swing of the output signal.

Abstract: A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.

Abstract: There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory.

Abstract: A controller for a DC/DC converter is provided. The controller comprises an error circuit, control logic, a high side driver, a low side driver, and an interface circuit. The error circuit is coupled to a feedback terminal so as to receives a feedback signal and is coupled to the control logic. The high side driver is coupled to the control logic and to a first output terminal so as to provide a first actuation signal, and the low side driver is coupled to the control logic and to a second output terminal so as to provide a second actuation signal. The interface circuit is also coupled to the control logic, including a first, second, and third voltage source, interface comparators, and current limited amplifier.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally employ capacitive digital-to-analog converters (CDACs) to perform data conversions. In these CDACs, matching of capacitive values is important, and for conventional high resolution SAR ADCs, complex trimming or calibration procedures can be too costly. Here, however, a SAR ADC is provided that performs error correction so as to reduce the overall cost compared to conventional SAR ADCs.

Abstract: In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable properties, such as reduced speed, ringing, latch-up, or lower electrostatic discharge (ESD) performance. Here, a mixed or hybrid mode driver is provided that employs a current steering circuit (instead of voltages driven differential pair(s) as is done with conventional drivers) to generate pull-down currents that precisely match the voltages in the pull-up portions of driver. It increases the speed and produces smaller output common-mode voltage fluctuation over conventional drivers. Thus, the driver provided here can be produced in BiCMOS process technologies without the undesirable effects of conventional drivers.

Abstract: An acoustic noise suppression filter including attenuation filtering with a noise-free estimate based on a codebook of line spectral frequencies.