Abstract: An image trap filter used in a radio frequency receiver for filtering an image signal from a radio frequency signal. The image trap filter includes an inductor and a capacitor connected in series in a first branch with the first branch connected in parallel with an impedance in a second branch. For low-side injection of the local oscillator signal (i.e., the frequency of the local oscillator signal is lower than the radio frequency signal), the impedance in the second branch is a capacitor and the series-connected inductor and capacitor in the first branch resonate at the frequency of the image signal and present a low impedance at the frequency of the image signal and a somewhat higher inductive impedance at the frequency of the radio frequency signal that resonates with the capacitor in the second branch at the frequency of the radio signal. For high-side injection of the local oscillator signal (i.e.

Abstract: A 6F2 memory cell structure and a method of fabricating the same. The memory cell structure includes a plurality of memory cells located in a Si-containing substrate which are arranged in rows and columns. Each memory cell includes a double-gated vertical MOSFET having exposed gate conductor regions and two gates formed on opposing sidewalls of the MOSFETs. The memory cell structure also includes a plurality of wordlines overlaying the double-gated vertical MOSFETs and in contact with the exposed gate conductor regions, and a plurality of bitlines that are orthogonal to the wordlines. Trench isolation regions are located adjacent to the rows of memory cells. The memory cell structure also includes a plurality of punch through stop regions located in the Si-containing substrate and self-aligned to the wordlines and bitlines. A portion of the punch through stop regions overlap each other under the bitlines and each region serves to electrically isolate adjacent buried-strap regions from each other.

Abstract: The present invention provides improved controllability of the lateral etch encroachment of silicon under the spacer, in light of the fact that the exemplary method, in accordance with the present invention, comprises the step of implanting neutral ions such as Ge or Ar into the source/drain regions. The implantation creates an amorphous silicon surface, and leaves a laterally extended amorphous layer under the spacer and a well defined amorphous/crystalline interface. The etch of silicon then extends laterally underneath the spacer, due to the higher etch rate of amorphous silicon and abrupt interface between amorphous and crystalline silicon.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: A MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.

Abstract: An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

Abstract: An apparatus and method for an electrodeposition or electroetching system. A thin metal film is deposited or etched by electrical current through an electrolytic bath flowing toward and in contact with a target on which the film is disposed. Uniformity of deposition or etching is promoted, particularly at the edge of the target film, by, baffle and shield members through which the bath passes as it flows toward the target. The baffle has a plurality of openings disposed to control the localized current flow across the cross section of the workpiece/wafer. Disposed near the edge of the target, the shield member shapes the potential field and the current line so that it is uniform.

Abstract: A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

Abstract: A cross-coupled voltage controlled oscillator having reduced phase noise. A pair of bipolar transistors having common emitter connections are coupled to reduce that oscillation frequency which is determined from a tuning circuit connected across the collectors of transistors. First and second varactor diodes provide analog tuning of the circuit, and a digitally controlled capacitor provides for a selection of a band of frequencies to be tuned by the varactor diodes. A current source provides the current to the emitter connections of the bipolar transistors. Second harmonic signals generated at the emitter of the transistors are significantly suppressed by a tuned filtered trap connected to the common emitter connections. By reducing the second harmonic signals, the phase noise or the voltage controlled oscillator can be significantly improved.

Abstract: A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.

Abstract: A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

Abstract: A process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a CMOS circuit with a gate. An intermediate semiconductor structure is provided having CMOS and bipolar areas. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack silicon layer is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the sacrificial layer from the CMOS area only such that the top surface of the sacrificial layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP) to form the raised extrinsic base.

Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.

Abstract: A method of fabricating a SiGe heterojunction bipolar transistor (HBT) is provided which results in a SiGe HBT that has a controllable current gain and improved breakdown voltage. The SiGe HBT having these characteristics is fabricated by forming an in-situ P-doped emitter layer atop a patterned SiGe base structure. The in-situ P-doped emitter layer is a bilayer of in-situ P-doped a:Si and in-situ P-doped polysilicon. The SiGe HBT structure including the above mentioned bilayer emitter is also described herein.

Abstract: A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, VT. Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired VT into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.

Abstract: The present invention includes methods and structures for forming at least a substantially self-aligned MOSFET. According to the present invention, a method of fabricating a semiconductor device includes providing a substrate; providing first materials (such as a first polysilicon) having horizontal surfaces and also having opposed vertical surfaces forming a trench; providing a second material (such as a second polysilicon) in the trench and over the vertical and horizontal surfaces, the second material having a substantially (eg, ±10%) uniform thickness so as to form a notch over the trench; providing a masking material (such as an oxide or a nitride) into the notch, and then removing the second material using the masking material as a mask in a direction toward the first material, so that a vertical surface of one of the first materials is at least substantially aligned with a vertical surface of the second material.

Abstract: A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.

Abstract: An electrodeposition apparatus for depositing material on a surface of a substrate. The electrodeposition apparatus includes at least one contact for vertically contacting the substrate and providing electrical connection to the substrate. The at least one contact does not scratch the surface of the substrate to be plated. A voltage source is connected to the at least one contact.

Abstract: A decoding scheme for simultaneously executing multiple operations for a stacked-bank type semiconductor memory device is disclosed. A decoding unit is provided to a memory bank group comprising a plurality of memory banks. When read and write bank addresses match with two different memory banks within the same memory bank group, the decoding unit receives the read and write addresses and generates two different row selection signals for the read and write operations in two different banks. Based on the row selection signals, the row decoder unit in the two matching banks simultaneously activates a target row designated by the read/write addresses.

Abstract: A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.