Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.

Abstract: Provided is an MRAM memory cell structure capable of preventing generation of parasitic transistors. Diodes are adopted as switching elements of an MRAM memory cell. An n-type semiconductor layer and a p-type semiconductor layer, which collectively constitute a diode, are formed on a surface semiconductor layer of an SOI substrate. The n-type semiconductor layer and the p-type semiconductor layer are disposed in a lateral direction and isolated by an isolation region, whereby the diode is isolated electrically from other elements and from the substrate.

Abstract: The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.

Abstract: An improved water soluble protective paste and a method for protecting metal circuits and pads on the surface of an electronic board during the manufacturing steps. A densifier is added to the paste making it easier and more efficient the dispensing of the paste. After deposition the layer is dried until a solid protective film is obtained. An additional advantage obtained by the present invention is that the protective layer can be deposited also by means of an offset printing process, avoiding the use of the stencil and of the screening steps. Screening process is a labourious operation which requires very sophisticated equipment and a very high precision in the design of the stencil. Because of these requirements, screening is an expensive process. On the other hand offset printing is a very simple, cheap and reliable method. In addition, the film forming properties allow the material to create a protective film even with a thin deposited film.

Abstract: A passive electrical device includes a first electrical conductor, a second electrical conductor disposed over the first conductor; and a third electrical conductor connecting the first conductor to the second conductor. The said first, second and third conductors are disposed on a semiconductor substrate. The sheet resistivity of the first conductor is approximately equal to the sheet resistivity of the second conductor.

Abstract: Method for the Manufacture of Micro Structures A method for the manufacture of micro structures in substrates is provided. The method uses a combination of photolithographic mask technology and micro contact printing.

Abstract: A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.

Abstract: A switch comprising a substrate, an elongated movable part, a pair of electrical contacts disposed at one side of said part, an actuation electrode disposed at the one side of the part and separated from the pair of electrical contacts, wherein the part, the contacts and the electrode are disposed on the substrate, wherein the elongated movable part is arranged and dimensioned such that the part is movable in a generally lateral direction toward the contacts; the movable part includes a central elongated member fixed to a head having an electrical contact disposed at the one side. One end of the movable part is attached to the substrate by means of various anchoring arrangements.

Abstract: A voltage controlled oscillator, comprising a pair of transistors connected to a tank circuit, said tank circuit including a plurality of tuning diodes connected in parallel with an inductor, said tuning diodes having cathodes connected to a common connection.

Abstract: To provide an inspection method for an EL array substrate that can detect a failure on the EL array substrate before assembling an EL panel. By giving a prescribed potential to a data line 6 to turn on a switching transistor 4 for a prescribed time, a holding capacitor 3 and a parasitic capacitor 8 are charged. By turning on again the switching transistor 4 after a lapse of a prescribed time from turning-off of the switching transistor 4 and by connecting the data line 6 to an integrator 10, the holding capacitor 3 and the parasitic capacitor 8 are discharged, and a discharged amount of charge is detected by the integrator 10. Based on this amount of charge, a failure on an EL array substrate is detected before assembling an EL panel.

Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.

Abstract: A switch comprising a substrate, an elongated movable part, a pair of electrical contacts disposed at one side of said part, an actuation electrode disposed at the one side of the part and separated from the pair of electrical contacts, wherein the part, the contacts and the electrode are disposed on the substrate, wherein the elongated movable part is arranged and dimensioned such that the part is movable in a generally lateral direction toward the contacts; the movable part includes a central elongated member fixed to a head having an electrical contact disposed at the one side. One end of the movable part is attached to the substrate by means of various anchoring arrangements.

Abstract: Bipolar integrated circuits employing SiGe technology incorporate the provision of mask-selectable types of bipolar transistors. A high-performance/high variability type has a thin base in which the diffusion from the emitter intersects the base dopant diffusion within the “ramp” of Ge concentration near the base-collector junction and a lower performance/lower variability type has an additional epi layer in the base so that the emitter diffusion intersects the Ge ramp where the ramp has a lower ramp rate.

Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.

Abstract: High quality factor (Q) inductor elements with dynamically driven, conductive, patterned shields are disclosed wherein a conductive, patterned shield structure/layer is provided between the inductor element and the substrate. The patterned shield is dynamically driven to the same electrical potential as the inductor element, to reduce or eliminate parasitic capacitive coupling between the inductor element and the conductive substrate. The patterned shield is patterned to form a plurality of conductive segments which are insulated from each other such that eddy currents cannot flow from one conductive segment to an adjacent conductive segment, to prevent the flow of eddy currents in the patterned shield when it is dynamically driven to the same electrical potential as the inductor element.

Abstract: A semiconductor memory structure having a feature size of less than about 90 nm which exhibits little or no dynamic charge loss and little or no trap assisted junction leakage is provided. Specifically, the semiconductor structure includes at least one back-to-back pair of trench storage memory cells present in a Si-containing substrate. Each memory cell includes a vertical transistor overlaying a trench capacitor. Strap outdiffusions are present on each vertical sidewall of the trench storage memory cells so as to interconnect the vertical transistor and the trench capacitor of each memory cell to the Si-containing substrate. A punchthrough stop doping pocket is located between each back-to-back pair of trench storage memory cells and it is centered between the strap outdiffusions of adjacent storage trenches, and self-aligned to the adjacent storage trenches.

Abstract: A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.

Abstract: A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.