Patents Represented by Attorney, Agent or Law Firm Juan Carlos A. Marquez, Esq.
  • Patent number: 6798486
    Abstract: A liquid crystal display device includes a pair of opposing substrates, a liquid crystal layer sandwiched between the opposing substrates, plural scanning signal lines disposed on one of the opposing substrates, plural video signal lines intersecting the plural scanning signal lines and disposed on the one of the opposing substrates, plural pixels arranged in a matrix formed by the plural scanning signal lines and the plural video signal lines, plural spacers for establishing a spacing between the opposing substrates, color filters disposed on another of the opposing substrates, and a planarizing film disposed over the color filters.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Yanagawa, Keiichiro Ashizawa, Masahiro Ishii, Masayuki Hikiba
  • Patent number: 6798671
    Abstract: The present invention provides a worldwide compatible switching power supply unit of an RCC system in which by reducing the number of components or parts, reduction of cost can be realized and the mounting space can be reduced. In a high input voltage and in a light load, an inductance of a primary winding of a transistor is set high but in the range of not exceeding a rated value of a main switching element, and in a low input voltage and in a heavy load, an inductance of a primary auxiliary winding and values of a control resistor and a capacitor of the main switching element are set low but in the range of not deteriorating the starting characteristics of the main switching element.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: September 28, 2004
    Assignee: Orion Electric Company, Ltd.
    Inventor: Hiroshi Sakai
  • Patent number: 6798509
    Abstract: The disclosed invention provides methods and instruments for fluorescence detection making it possible to separate and detect analytes of a plurality of species in a migration (separation) channel with length of the order of millimeters. Analyte samples disperse across the whole detection region of a migration channel filled with a sieving matrix. Electrodes located in contact with a power supply and the sieving matrix cause the analytes to electophoretically migrate at predetermined velocity V. The detection region is irradiated by excitation light whose intensity changes in a cycle equaling pitch p in the direction that the analytes move. Fluorescence emission from the analytes exposed to the excitation light is detected by a detector. Fluctuation &dgr;i (t) of output current from the detector is analyzed by a spectrum analyzer and the obtained spectrum is displayed.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: September 28, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Sonehara, Kyoko Kojima, Takashi Irie
  • Patent number: 6795358
    Abstract: Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: September 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yousuke Tanaka, Tomofumi Hokari, Masatoshi Hasegawa
  • Patent number: 6794663
    Abstract: A sample fabricating method of irradiating a sample with a focused ion beam at an incident angle less than 90 degrees with respect to the surface of the sample, eliminating the peripheral area of a micro sample as a target, turning a specimen stage around a line segment perpendicular to the sample surface as a turn axis, irradiating the sample with the focused ion beam while the incident angle on the sample surface is fixed, and separating the micro sample or preparing the micro sample to be separated. A sample fabricating apparatus for forming a sample section in a sample held on a specimen stage by scanning and deflecting an ion beam, wherein an angle between an optical axis of the ion beam and the surface of the specimen stage is fixed and formation of a sample section is controlled by turning the specimen stage.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: September 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyasu Shichi, Tohru Ishitani, Hidemi Koike, Kaoru Umemura, Eiichi Seya, Mitsuo Tokuda, Satoshi Tomimatsu, Hideo Kashima, Muneyuki Fukuda
  • Patent number: 6794678
    Abstract: Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: September 21, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masatoshi Hasegawa, Shuichi Miyaoka, Hiroshi Akasaki, Masahiro Katayama
  • Patent number: 6793476
    Abstract: A work table supports a grid of green brick aligned in longitudinal and transverse row for indexing movement by a hydraulic cylinder actuated pusher. The brick are indexed longitudinally beneath a first transverse row of embossing devices in a transverse row aligned with one embossing device being over every other brick of the transverse row. Following actuation of the first transverse row of embossing devices the brick are indexed beneath a second transverse row of embossing devices each of which is aligned with the brick that were not embossed by the first transverse row of embossing devices. Ramps are provided below the rows of embossing devices to elevate the brick above the next adjacent rows so that the brick being embossed is at a higher elevation than the adjacent brick.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: September 21, 2004
    Assignee: General Shale Products LLC
    Inventors: James G. Bryja, Robert W. O'Quinn, Robert W. Keyes
  • Patent number: 6793459
    Abstract: A water pump includes a body, a fixing member to which the body is fixed hermetically via a gasket, and an impeller which is fixed to an end part of a shaft supported rotatably by the body and housed in a vortex chamber formed in the body or in the fixing member. Further, the impeller has a circular plate into which the end part of the shaft is inserted and a plurality of blades radially provided on the circular plate at one side facing the fixing member or the other side facing the body and project from the circular plate to the fixing member side or the body side. In the water pump, the gasket has an intermediate plate with high rigidity and metal gaskets disposed between the intermediate plate and the body, and between the intermediate plate and the fixing member for sealing. The intermediate plate extends in radial direction to keep a predetermined axial distance between an inner peripheral portion of the intermediate plate and an end part of the blades facing to the fixing member or to the body.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: September 21, 2004
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Masaki Chujo, Yoshiaki Nakano, Atsushi Chiba, Shuhei Yamazaki
  • Patent number: 6794961
    Abstract: A high frequency circuit module for use in an automotive radar or the like, in which RF circuit parts are mounted on both sides of a hard multilayer dielectric substrate, and a transmission line connecting the RF circuit parts provided on both sides is constructed by a via group including a periodical structure or a via having a coaxial structure perpendicular to faces of the multilayer dielectric substrate. As the multilayer dielectric substrate, a hard multilayer substrate using metallic layers as a microstrip line wiring layer, a DC/IF signal line layer, and grounding metal layers for shielding which are disposed on and under the DC/IF signal line is employed. By using the transmission line achieved by a through via having the periodical structure or the through via having the coaxial structure, an electromagnetic wave propagating in parallel between the grounding conductors is confined.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: September 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Nagaishi, Hiroshi Kondoh
  • Patent number: 6795368
    Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: September 21, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
  • Patent number: 6793361
    Abstract: A reflector for each of linear light sources arranged in parallel at predetermined intervals. The reflector is arranged symmetrically about each linear light source and consisting of three reflective surfaces to reflect light back to three regions of the surface to be illuminated. The first reflective surface is flat horizontal and closest to the light source to reflect light back to a relatively wide range. The second reflective surface is slanted to the horizontal reflective surface to reflect light overlapped with the reflected light by the first reflective surface. The third reflective surface is farthest from the light source and slanted to the horizontal reflective surface so as to reflect light overlapped with the reflected light by the first reflective surface.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: September 21, 2004
    Inventor: Hirokazu Matsui
  • Patent number: 6795150
    Abstract: The liquid crystal display device which can prevent the lowering of the aperture rate irrespective of the misalignment of substrates is disclosed. The liquid crystal display device includes a black matrix and respective electrodes which are formed along respective opposing sides of an aperture portion of the black matrix, and respective electrodes are formed in patterns where irrespective of the misalignment of the black matrix in the widthwise direction of the electrodes, the light transmitting region within the aperture portion of the black matrix is made substantially constant.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: September 21, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Yanagawa, Masuyuki Oota, Keiichiro Ashizawa, Masayuki Hikiba
  • Patent number: 6790564
    Abstract: In the step of manufacturing a photomask, an opaque pattern is formed by using a photosensitive resin composition containing a specified light absorbent, which then used to manufacture a photomask for KrF excimer laser lithography in a short manufacturing time and at a reduced cost. Accordingly, the manufacturing time and the cost for semiconductor integrated circuit devices is reduced.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Sonoko Migitaka, Tadashi Arai, Tsutomu Araki, Satoshi Momose, Osamu Yamaguchi
  • Patent number: 6792498
    Abstract: Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Nakamura, Hidetaka Aoki
  • Patent number: 6791934
    Abstract: When it is intended to realize a lens having a large NA with one lens, an adjustment precision between both surfaces of the lens is very strict. Accordingly an objective lens having an NA of 0.8 or more was usually realized by two lenses. However, a working distance is small, and collision of the objective lens with a disc is apt to occur. A coma corrector for compensating coma caused by decentering of both surfaces in realizing the high NA lens with one lens is added. However, in this case, astigmatism occurs when the objective lens decenters from the coma corrector relatively accompanied with a tracking operation. The objective lens and the coma corrector are fixed to a mirror barrel so as to be unified with each other, and driven by a two-dimensional lens actuator. With such a constitution, decentering of the objective lens and the coma corrector does not occur, and hence astigmatism does not occur.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., PENTAX Corporation
    Inventors: Takeshi Shimano, Tetsuo Ariyoshi, Kazuo Shigematsu, Koichi Maruyama, Shuichi Takeuchi
  • Patent number: 6790651
    Abstract: According to the present invention, hybridization reaction and washing steps can be carried out continuously without taking out the substrate from the apparatus, thereby simplifying manipulation of the experiment. A reaction solution or a washing solution is injected with a pump 6 and discharged with a pump 22 into and from a case 3 which accommodates a substrate 1 immobilized with biological substances. As the substrate 1, a disc-shaped substrate with a throughhole at the center is used. An agitator 2 is placed in the throughhole to agitate the reaction solution or the washing solution during the hybridization reaction or the subsequent washing, thereby shortening the reaction time and the washing time.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: September 14, 2004
    Assignee: Hitachi Software Engineering Co., Ltd.
    Inventors: Toshiaki Tanaka, Mitsuhiro Tachibana, Shigeru Kijima
  • Patent number: 6791877
    Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Seiji Miura, Kazushige Ayukawa
  • Patent number: 6791256
    Abstract: A display device includes a first substrate, a second substrate disposed to face the first substrate, plural pixels disposed in a display area on an inner surface of the first substrate, a rubber member disposed between the first and second substrates to surround the display area, and sealing the display area from an ambient atmosphere, and an adhesive layer sealing together the first and second substrates along peripheries thereof. The adhesive layer is derived from a sol-gel solution.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: September 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Nishizawa, Noriharu Matsudate, Norikazu Uchiyama, Maki Taniguchi
  • Patent number: 6791895
    Abstract: A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Keiichi Higeta, Shigeru Nakahara, Hiroaki Nambu
  • Patent number: 6788792
    Abstract: An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: September 7, 2004
    Assignee: Yamaha Corporation
    Inventors: Toshio Maejima, Masao Noro