Patents Represented by Attorney, Agent or Law Firm Juan Carlos A. Marquez, Esq.
  • Patent number: 6773901
    Abstract: Adenylation of a DNA fragment with a DNA polymerase occurs in the course of PCR, and thus two peaks are detected. To prevent the peak splitting, it is necessary to raise efficiency of adenylation a single peak to occur without changing reaction conditions. To this end, four types of PCR primers which, respectively, have an anchor sequence at 5′ terminus so that any of A, C, G or T is attached to at the 5′ terminus of the anchor sequence, and PCR is carried out by use of the respective primers to determine efficiencies of adenylation. Subsequently, an anchor sequence that is more likely to undergo adenylation is screened to decide an anchor sequence more likely undergo adenylation, followed by PCR by use of a primer having the decided anchor sequence.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: August 10, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Chihiro Uematsu, Kazunori Okano, Takashi Irie
  • Patent number: 6771535
    Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the-amplified current to an associated read data line.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka, Katsuro Watanabe, Kenchi Ito
  • Patent number: 6770492
    Abstract: This invention provides a technique for preventing film quality of a capacitive insulating film made of a ferroelectric film of a FeRAM memory cell from being degraded and for improving the characteristics of the FeRAM memory cell. A shielding film having a higher lead content than that of a capacitive insulating film is formed under a lower electrode of a capacitor in a FeRAM memory cell, and another shielding film having a higher lead content than that of the capacitive insulating film is formed on an upper electrode. PZT films to be used as barrier layers are formed in the interlayer insulating films the FeRAM memory cell. As a result, it is possible to prevent H2 or H2O from entering an upper portion or a lower portion of the capacitor, and lead diffused from the capacitive insulating film 11a can be compensated by lead included in the shielding films, and it is possible to prevent characteristics of the capacitive insulating film 11a from being degraded.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: August 3, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Hiromichi Waki, Keiichi Yoshizumi, Mitsuhiro Mori
  • Patent number: 6772403
    Abstract: This is a method for more accurately calculating delay times in an electronic circuit device wherein signal arrival times on a victim wire and a plurality of aggressor wires adjacent thereto dynamically vary dependent on an input signal pattern by analyzing values of crosstalk-deriving delay degradation occurring between those wires. By utilizing delay degradation information searchable according to relative signal arrival times between the victim wire and the aggressor wires and adding delay degradations arising between the victim wire and the aggressor wires, calculated at every signal arrival time on the victim wire, the total delay degradation in the presence of a plurality of aggressor wires is calculated. Designing of a high-speed and large-scale electronic circuit device is facilitated and, because a superfluous margin regarding delay times can be eliminated, such electronic circuit devices can be efficiently designed and manufactured.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventor: Yasuhiko Sasaki
  • Patent number: 6770528
    Abstract: Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film 26A is deposited in the trenches 25 made in a silicon oxide film 24. A photoresist film 30 is then formed on the amorphous silicon film 26A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film 30, thereby exposing to light those parts of the photoresist film 30 which lie outside the trenches 25. The other parts of the photoresist film 30, which lie in the trenches 25 are not exposed to light because the light reaching them is inadequate. Further, the photoresist film 30 is developed thereby removing those parts of the film 30 which lie outside the trenches 25 and which have been exposed to light. Thereafter, those parts of the amorphous silicon film 26A, which lie outside the trenches 25, are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film 30 which remain in the trenches 25.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 3, 2004
    Assignees: Hitachi ULSI Systems Co., Ltd., Renesas Technology Corp.
    Inventors: Ryouichi Furukawa, Kazuyuki Suko, Masayuki Hiranuma, Koichi Saitoh, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Maki Shimoda
  • Patent number: 6771332
    Abstract: A flexible substrate mounting the light sources thereon realizes a shape which can eliminate a largely projecting portion and a liquid crystal display device which uses such a flexible substrate is obtained. A strip-like portion is formed by providing an elongated cut in a flexible substrate and light sources are mounted on the strip-like portion. Due to such a constitution, the strip-like portion mounting the light sources 5 thereon has a shape which is substantially arranged parallel to the shape of the main portion 8 which occupies a most portion of the flexible substrate land hence, it is possible to eliminate a largely projecting portion. Then, the light sources 5 are arranged such that the strip-like portion is folded back at least once such that light from the light sources is incident on a light guide body 4.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: August 3, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventor: Takahiro Yamada
  • Patent number: 6772426
    Abstract: The disk carrier device of the present invention comprises a carrier gear rotation-driven by a motor, control members driven by the motor via this carrier gear, for moving in one direction or in the other direction according to the direction of rotation of the motor, and a transmission gear which transmits the rotation of the motor to a feed roller. A rotation control section and a roller position control section are provided in the control member, respectively. At the time of ejecting the disk, with the movement of the control member, the feed roller is made to approach the disk guide by the roller position control section, and then the transmission gear is shifted to the transmission position by the rotation control section.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: August 3, 2004
    Assignee: Tanashin Denki Co., Ltd.
    Inventor: Shigeru Akatani
  • Patent number: 6767748
    Abstract: The present invention enables the accurate management of the total number of spotting counts for each spotting pin. An IC chip is installed on the spotting pin to allow the IC chip to accumulate spotting-count information, and during each spotting time the information is loaded up and displayed.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: July 27, 2004
    Assignee: Hitachi Software Engineering Co., Ltd.
    Inventors: Naoki Yokokawa, Mitsuhiro Tachibana, Hiroshi Kishida
  • Patent number: 6768531
    Abstract: A pair of electrodes which constitute an upper layer and a lower layer with respect to an interlayer insulation film are formed as different layers at respective pixel regions on a liquid-crystal-side surface of one substrate out of respective substrates which are arranged to face each other in an opposed manner by way of liquid crystal. At two pixel regions which are selected from the respective pixel regions, the height of background layers on which the electrodes which constitute the lower layers with respect to the interlayer insulation films are formed differs with respect to a surface of one substrate. The film thickness of the interlayer insulation film is set small with respect to the high background layer out of respective background layers which differ in height and is set large with respect to the low background layer out of respective background layers which differ in height.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: July 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Ochiai, Kikuo Ono, Ryutaro Oke, Kazuhiko Yanagawa
  • Patent number: 6764278
    Abstract: A water, pump includes a driven portion, a shaft connected to the driven portion, an impeller connected to the shaft, and a body supporting the driven portion for relative rotation therewith. The water pump is characterized in that the driven portion and the shaft are formed integrally by resin molding, and an outer surface of the bearing is fixed to the driven portion.
    Type: Grant
    Filed: May 22, 2002
    Date of Patent: July 20, 2004
    Assignee: Aisin Seiki Kabushiki Kaisha
    Inventors: Yasuo Ozawa, Junya Yamamoto
  • Patent number: 6765193
    Abstract: Optical touch switches are implemented based on the use of light total internal reflection and light scattering concepts. The optical touch switch basically consists of a light source, a light guide, a photodetector, and an electronic controller. The fingertip touching on the touching surface of the optical touch switch leads to the change in electrical current produced by the photodetector. As a result, the electronic control box senses this change of electrical current and allows the electrical load to stay at the desired state. Key advantages include ease of implementation, prevention of the light beam incident directly on the user's eyes, and ability to accept both strong and weak mechanical forces from users.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: July 20, 2004
    Assignee: National Science and Technology Development Agency
    Inventor: Sarun Sumriddetchkajorn
  • Patent number: 6765434
    Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: July 20, 2004
    Assignee: Renesas Technology Corporation
    Inventor: Hiroyuki Mizuno
  • Patent number: 6762802
    Abstract: The present invention provides a novel photolithography processes using photoresist pattern having at least two areas which has different thickness from each other for a fabrication method for a liquid crystal display device having reversed staggered and channel-etched type thin film transistors, reduce a number of photolithography processes required for whole of the fabrication process of the liquid crystal display device, and improve brightness of the liquid crystal display device.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: July 13, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kikuo Ono, Yoshiaki Nakayoshi, Ryutaro Oke, Toshiki Kaneko
  • Patent number: 6762963
    Abstract: A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines. An address selecting circuit switches the defective word line to a redundant word line according to the evaluation result. The redundancy relief circuit then evaluates whether a refresh address added to the refresh address signal corresponds to a defective address, and during refresh, the address selecting circuit selects a normal or redundant word line according to the evaluation result in a preceding cycle.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: July 13, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshihiko Inoue, Hisashi Motomura, Masashi Horiguchi
  • Patent number: 6762111
    Abstract: Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: July 13, 2004
    Assignee: Renesas Technology Corporation
    Inventor: Hiroshi Fukuda
  • Patent number: 6762444
    Abstract: In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: July 13, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Fumio Ootsuka, Yusuke Nonaka, Satoshi Shimamoto, Sohei Omori, Hideto Kazama
  • Patent number: 6762551
    Abstract: A white light source includes an ultraviolet-visible excitation light generation unit capable of generating visible light and ultraviolet light, and a fluorescence generation unit having a phosphor layer and being capable of generating visible light upon excitation by the ultraviolet light and uses, in the phosphor layer, a red light emitting phosphor represented by the following compositional formula: (Ca1−a−bSraEub)S:Mc, wherein a, b and c satisfy the following conditions: 0≦a<1.0, 0≦b<0.1 and 0≦c≦0.1; and M is a dopant element having absorption of excitation energy at about 350 nm to about 500 nm. The dopant element M includes rare earth elements such as Ce, Yb, Gd and Tm. By substituting part of Ca and/or Sr with Zn, the white light source can exhibit further improved performances.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: July 13, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Shiiki, Masaaki Komatsu, Choichiro Okazaki, Shin Imamura, Teruki Suzuki
  • Patent number: 6762969
    Abstract: A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: July 13, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Toshio Sasaki, Toshio Yamada
  • Patent number: D492878
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: July 13, 2004
    Assignee: Joytec Corporation
    Inventors: Yutaka Nakato, Noriyuki Kobayashi
  • Patent number: D493724
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: August 3, 2004
    Inventor: Mitsuo Higuchi