Abstract: A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.

Abstract: A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Abstract: A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

Abstract: A photosensitive monomer including a methylene butyrolactone derivative represented by the following formula: wherein R1 is a hydrogen atom or alkyl group, R2 is an acid-labile group, X is a hydrogen atom, or substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, and Y is a substituted or unsubstitued alkyl group or alicyclic hydrocarbon group having 1 to 20 carbon atoms.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A monolithic ink-jet printhead, and a method for manufacturing the same, wherein the monolithic ink-jet printhead includes a manifold for supplying ink, an ink chamber having a hemispheric shape, and an ink channel formed monolithically on a substrate; a silicon oxide layer, in which a nozzle for ejecting ink is centrally formed in the ink chamber, is deposited on the substrate; a heater having a ring shape is formed on the silicon oxide layer to surround the nozzle; a MOS integrated circuit is mounted on the substrate to drive the heater and includes a MOSFET and electrodes connected to the heater. The silicon oxide layer, the heater, and the MOS integrated circuit are formed monolithically on the substrate. Additionally, a DLC coating layer having a high hydrophobic property and high durability is formed on an external surface of the printhead.

Abstract: A burst mode receiving apparatus having an offset compensating function and a data recovery method thereof, including an intermediate value detector to detect and output an intermediate value of an input signal input from an outside source in response to a switching control signal; an amplifier to amplify and output a difference between the input signal and a reference value; an offset compensator to generate a compensation signal having a level varied corresponding to the amplified result input from the amplifier and a compensation control signal; a summing portion to add the compensation signal and the intermediate value to output the added result as the reference value to the amplifier; and a controller to generate the switching control signal and the compensation control signal corresponding to a result obtained by analyzing the amplified result input from the amplifier and a reset signal input from the outside source.

Abstract: A metal contact structure of a semiconductor device and a method for forming the same, wherein an upper conductive layer is formed by etching a metal layer, which fills a contact hole and is formed on the entire surface of an interlayer dielectric film and etching is stopped when barrier metal layers under the metal layer is exposed. Then, after forming spacers on the sidewalls of an upper conductive layer, the barrier metal layers (a barrier layer and an ohmic layer) are removed using the spacers as etching masks. Therefore, it is possible to prevent problems due to etch mask misalignment, such as 1) an etching gas of the metal layer permeating through the ohmic layer and 2) defects such as contact resistance changes that occur when spacers cover a contact hole even though the upper conductive layer does not completely cover that contact hole.

Abstract: A bubble-jet type ink-jet printhead, a manufacturing method thereof and a method of ejecting ink, wherein, in the printhead, a manifold supplying ink, a hemispherical ink chamber, and an ink channel for connecting the manifold with the ink chamber are integrally formed on the substrate. A nozzle plate on the substrate having a nozzle, and a heater formed in an annular shape and centered around the nozzle are integrated without a complex process such as bonding. Thus, this simplifies the manufacturing process and facilitates high volume production. Furthermore, according to the ink ejection method, a doughnut-shaped bubble is formed to eject ink, thereby preventing a back flow of ink as well as formation of satellite droplets that may degrade image resolution.

Abstract: A catalyst, method, and exhaust system for purifying exhaust gas from vehicle engines, including a catalyst having a carrier doped with copper oxide (CuO), and a precious metal as a main catalyst is disclosed. The impregnation of copper oxide into the carrier protects the catalyst from damage due to the toxicity of exhaust gas, and hinders agglomeration of precious metal particles used as the main catalyst. As a result, the heat resistance of the catalyst at high temperatures in addition to the catalytic activity for the oxidation of particulates can be improved.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Abstract: A method for manufacturing an ink-jet printhead having a hemispherical ink chamber, wherein a nozzle plate is formed on a surface of substrate; a heater is formed on the nozzle plate; a manifold for supplying ink; an electrode is formed on the nozzle plate to be electrically connected to the heater; a nozzle is formed by etching the nozzle plate inside the heater; a groove for forming an ink channel is formed to expose the substrate so that the groove extends from the outside of the heater toward the manifold; an ink chamber is formed to have a diameter greater than the diameter of the heater and be hemispherical by etching the substrate exposed by the nozzle; an ink channel is formed to be in flow communication with the ink chamber and the manifold; and the groove is closed by forming a material layer on the nozzle plate.

Abstract: A photosensitive polymer including a copolymer of an acrylate or methacrylate monomer having a group indicated by the following formula (I), a comonomer selected from a maleic anhydride monomer and a cyclic vinyl ether monomer, and a resist composition including the same. In the formula, R1, R2, R3, and R4 are independently a hydrogen atom, a C1-C4 alkyl group, a C1-C4 alkoxy group, a phenyl group, a benzyl group, a phenoxy group, or —M(R′)3, M is Si, Ge, Sn, or OSi, and each R′ independently is a C1-C4 alkyl group, a C1-C4 alkoxy group, a phenyl group, or a phenoxy group.

Abstract: A method for fabricating a semiconductor device and a semiconductor formed by this method, the method including, the steps of sequentially forming a pad oxide film, a polysilicon film, and an antioxidation film on an active region of a semiconductor substrate such that a field region is exposed; etching an exposed portion of the surface of the substrate to a predetermined thickness to form a trench within the substrate; forming a first insulation film along the inner face of the trench by using an oxidation process; forming a stress buffer film on the entire surface of the resultant structure; forming a second insulation film on the stress buffer film such that the trench is sufficiently filled; making the second insulation film planar such that the remaining antioxidation film has a predetermined thickness on the active region of the substrate so as to form a shallow trench isolation within the trench; and sequentially removing the remaining antioxidation film, the polysilicon film, and the pad oxide film.

Abstract: A bubble-jet type inkjet printhead is disclosed, wherein a manifold for supplying ink, an ink chamber having a substantially hemispherical shape and filled with ink to be ejected, and an ink channel for supplying ink from the manifold to the ink chamber, are incorporated in a substrate. A nozzle plate having a nozzle, through which ink is ejected at the center of the ink chamber, is formed on the substrate. A heater is provided on the nozzle plate and surrounding the nozzle, and electrodes are provided on the nozzle plate and electrically connected to the heater to supply pulse current to the heater. An anti-wetting coating including a perfluorinated alkene compound on at least a surface around the nozzle is formed on an exposed surface of the printhead. Preferably, the anti-wetting coating is deposited by RF glow discharge and can be removed by O2 plasma.

Abstract: The present invention relates to metal interconnections for bit lines having a low resistance and an advanced morphology and a method of forming the same including: forming an inter-layer insulation film on a semiconductor substrate, the inter-layer insulation film containing a contact hole for the bit line; forming a plug within the contact hole; forming a barrier metal defined on the plug; and forming a bit line on the inter-layer insulation film.

Abstract: A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

Abstract: A method for manufacturing a cell capacitor includes a step of forming an upper electrode and a trench for the lower electrode simultaneously in a single mask step. Further steps for manufacturing a cell capacitor includes forming a storage node contact by employing a predefined plate silicon layer and forming a capacitor dielectric using the storage contact node, as a result, it becomes possible to resolve “lift-off” problems, twin-bit failures, and misalignment.

Abstract: A single electron memory device including quantum dots between a gate electrode and a single electron storage element and a method for manufacturing the same, wherein the single electron memory device includes a substrate on which a nano-scale channel region is formed between a source and a drain, and a gate lamination pattern including quantum dots on the channel region. The gate lamination pattern includes a lower layer formed on the channel region, a single electron storage medium storing a single electron tunneling through the lower layer formed on the lower layer, an upper layer including quantum dots formed on the single electron storage medium, and a gate electrode formed on the upper layer to be in contact with the quantum dots.

Abstract: A method for forming alignment keys on the scribe line areas of a semiconductor wafer. An etch blocking layer is used to reduce the depth of the channels forming the alignment key. One of the layers of material deposited on the semiconductor wafer to form integrated circuit devices on the wafer may be used as the etch blocking layer. A portion of this layer of material may be left intact on the scribe line areas during the manufacturing process. The subsequently deposited layers have an etch selectivity with respect to the etch blocking layer and the subsequently deposited layers are etched down to the etch blocking layer to form the alignment keys.