Patents Represented by Attorney Martine, Penilla & Gencarella, LLP
  • Patent number: 7997288
    Abstract: A system for processing a substrate is described. The system includes a proximity head, a mechanism, and a liquid supply. The proximity head is configured to generate a controlled meniscus. Specifically, the proximity head has a plurality of dispensing nozzles formed on a face of the proximity head. The dispensing nozzles are configured to supply a liquid to the meniscus and the suction holes are added to remove a used liquid from the meniscus. The mechanism moves the proximity head or the substrate with respect to each other while maintaining contact between the meniscus and a surface of the substrate. The movement causes a thin layer of the liquid to remain on the surface after being contacted by the meniscus.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 16, 2011
    Assignee: Lam Research Corporation
    Inventors: Mike Ravkin, Alex Kabansky, John de Larios
  • Patent number: 7997289
    Abstract: Discs roll along an inclined track through a chamber to expose opposite disc sides for cleaning. Energized fluid directed against the opposite sides removes particles from the discs, the fluid and particles exiting the chamber. Stop pins control a time period for cleaning and transporting the discs by selectively blocking or releasing the discs. The discs are stopped at many sections of a transducer, the sections being tailored to provide various cleaning characteristics. Within the chamber, the chamber is configured to minimize particles that originate other than by being adhered to the disc at a time when the disc is introduced into the chamber. Internal chamber configuration also minimizes retention of particles so that particles removed from one disc do not linger in the chamber for possible transfer to a disc that is cleaned in the same chamber at a later time.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: August 16, 2011
    Assignee: Xyratex Technology Limited
    Inventors: Dave Frost, Sean Harbison, Yassin Mehmandoust, Mike Frocappa
  • Patent number: 7995637
    Abstract: One aspect of the disclosed subject matter describes a gas discharge laser chamber. The gas discharge laser chamber includes a discharge region formed between a first electrode and a second electrode, a tangential fan for circulating gas through the discharge region, wherein the fan is proximate to an input side of the discharge region, an input side acoustic baffle proximate to the input side of the discharge region. The input side acoustic baffle includes a vanishing point leading edge, a vanishing point trailing edge, a gas flow smoothing offset surface aligning a gas flow from a surface of the input side acoustic baffle to an input side of a cathode support in the discharge region, a plurality of ridges separated by a plurality of trenches, wherein the plurality of ridges and the plurality of trenches are aligned with a direction of gas flow through the discharge region and wherein the plurality of ridges have a random pitch between about 0.3 and about 0.7 inch.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: August 9, 2011
    Assignee: Cymer, Inc.
    Inventors: Richard L. Sandstrom, William N. Partlo, Daniel J. W. Brown, Bryan G. Moosman, Tae H. Chung, Thomas P. Duffey, James J. Ferrell, Terance Hilsabeck
  • Patent number: 7994545
    Abstract: Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: August 9, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Michael C. Smayling, Scott T. Becker
  • Patent number: 7995773
    Abstract: A method for processing an audio signal received through a microphone array coupled to an interfacing device is provided. The method is processing at least in part by a computing device that communicates with the interfacing device. The method includes receiving a signal at the microphone array and applying adaptive beam-forming to the signal to yield an enhanced source component of the signal. Also, an inverse beam-forming is applied to the signal to yield an enhanced noise component of the signal. The method combines the enhanced source component and the enhanced noise component to produce a noise reduced signal, where the noise reduced signal is a target voice signal. Then, monitoring an acoustic set-up associated with the audio signal as a background process using the adaptive beam-forming inverse beam-forming to track the target signal component, and periodically setting a calibration of the monitored acoustic set-up.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: August 9, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Xiadong Mao
  • Patent number: 7996580
    Abstract: A host device includes an electrical activity monitoring (EAM) module that is configured to monitor the electrical activity of a slave storage device interfaced with the host device. Responsive to the value of, or change in, the electric current fed to the slave storage device being at or near a certain level, or within a predetermined range, the EAM module notifies the host device that the slave storage device has pending service request(s) or information for the host device.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: August 9, 2011
    Assignee: SanDisk IL Ltd.
    Inventors: Micha Rave, Nir Perry
  • Patent number: 7989847
    Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: August 2, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 7990235
    Abstract: The present invention is directed to a transmission line assembly and method of propagating signals therethrough that features forming transmission lines of the assembly to provide desired filtering properties. To that end, the assembly includes a plurality of spaced-apart transmission lines placing first and second sets of active circuits in electrical communication, with a subset of the plurality of spaced apart transmission lines having dimensions to filter unwanted characteristics of signals, propagating between the first and second sets and inductively coupled between one or more of the plurality of spaced-apart transmission lines. The method performs the function of the assembly.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 2, 2011
    Assignee: Altera Corporation
    Inventors: Yee Huan Yew, Hong Shi
  • Patent number: 7990183
    Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 2, 2011
    Assignee: Advantest Corporation
    Inventor: Shoji Kojima
  • Patent number: 7989942
    Abstract: An integrated circuit (IC) package with a plurality of chip capacitors placed on a surface of a die is disclosed. The chip capacitors may be placed on top of the die with an interposal substrate layer. Placing chip capacitors on top of the die may reduce the size of the packaging substrate required. One or more wires may be used to connect the chip capacitors on the interposal layer to the packaging substrate. The IC package may include a lid and a thermal interface material (TIM) placed on top of the die. The lid may be shaped such that a protruding portion of the lid contacts the die directly through the TIM to improve heat dissipation.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: August 2, 2011
    Assignee: Altera Corporation
    Inventors: Teik Tiong Toong, Loon Kwang Tan
  • Patent number: 7990764
    Abstract: A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 2, 2011
    Assignee: SanDisk IL Ltd.
    Inventors: Idan Alrod, Eran Sharon
  • Patent number: 7989848
    Abstract: A substrate portion of a semiconductor device is formed to include a plurality of diffusion regions that are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The conductive features within the gate electrode level region are defined along at least four different virtual lines of extent in the first parallel direction. A width size of the conductive features within the gate electrode level region is measured perpendicular to the first parallel direction and is less than a wavelength of light used in a photolithography process to fabricate the conductive features.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: August 2, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 7987261
    Abstract: Methods, apparatuses and systems directed to predicting the performance of an information package or module presented on a network addressable resource, such as a web page. A particular implementation relies on regression models that utilize statistical measures of user interest in terms, concepts and other subject matter as revealed in on-line search activity of a pool of users. A model receives as inputs a plurality of attribute values corresponding to an information package or module (including one or more statistical measures of interest) and outputs an estimated click-thru rate.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: July 26, 2011
    Assignee: Yahoo! Inc.
    Inventor: Nathan E. Gamble
  • Patent number: 7983414
    Abstract: In a method for protected execution of a cryptographic calculation in which a key with at least two key parameters is drawn on, an integrity check of the key is performed, in order to prevent a cryptographic attack in which conclusions are drawn as to at least one second key parameter by corrupting at least one first key parameter. A further method serves to determine a key for a cryptographic calculation with at least two key parameters provided for use in the first-mentioned method. A computer program product and a portable data carrier have corresponding features. The methods enable particularly good protection of cryptographic calculations against attacks.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: July 19, 2011
    Assignee: Giesecke & Devrient GmbH
    Inventors: Markus Bockes, Hermann Drexler, Helmut Kahl
  • Patent number: 7983880
    Abstract: Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Joshua David Fender, Paul Leventis
  • Patent number: 7981753
    Abstract: A device for providing electrostatic discharge (ESD) protection is provided. The device includes a semiconductor substrate having a drain, a source, and a gate formed therein. The drain contains a region having a resistance that is higher than the resistance of the remainder of the drain and the source. The gate region is in contact with this higher resistance region and the source. In one embodiment, the higher resistance is lacking silicide in order to provide the higher resistance. A method of forming a device for providing ESD protection is included.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: July 19, 2011
    Assignee: Altera Corporation
    Inventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
  • Patent number: 7981307
    Abstract: A method for etching a bevel edge of a substrate in a processing chamber is provided. The method includes flowing an inert gas into a center region of the processing chamber defined above a center region of the substrate and flowing a mixture of an inert gas and a processing gas over an edge region of the substrate. The method further includes striking a plasma in the edge region, wherein the flow of the inert gas and the flow of the mixture maintain a mass fraction of the processing gas substantially constant. A processing chamber configured to clean a bevel edge of a substrate is also provided.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: July 19, 2011
    Assignee: Lam Research Corporation
    Inventors: Jack Chen, Andrew D. Bailey, III, Iqbal Shareef
  • Patent number: 7979067
    Abstract: Methods and systems for generating information about a physical context of a user are provided. These methods and systems provide the capability to render a context avatar associated with the user as a composite image that can be broadcast in virtual environments to provide information about the physical context of the user. The composite image can be automatically updated without user intervention to include, among other things, a virtual person image of the user and a background image defined by encoded image data associated with the current geographic location of the user.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: July 12, 2011
    Assignee: Yahoo! Inc.
    Inventor: Rahul Nair
  • Patent number: 7978493
    Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: July 12, 2011
    Assignee: Altera Corporation
    Inventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua
  • Patent number: 7978247
    Abstract: The focusing information visualization system of the invention extracts an edge having an edge intensity of not less than a first reference value Th1 and an edge width of not greater than a second reference value Th2 in a photographic image and displays the extracted edge in a preset color at a position of the edge extraction to be overlapped with the original photographic image on a screen. A focused area defined by the extracted edge is displayed as N divisional areas. In response to a user's operational specification of one divisional area among the N divisional areas, an enlarged photographic image corresponding to the specified divisional area at a desired magnification ratio is displayed on the screen. This arrangement adopts the automatic rough judgment and the user's final visual check to accurately recognize the focusing status of the photographic image.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: July 12, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Ayahiro Nakajima, Naoki Kuwata, Kenji Matsuzaka, Seiji Aiso