Patents Represented by Attorney McGinn & Gibb, PLLC
  • Patent number: 6927720
    Abstract: An analog signal outputting circuit comprises two unit analog circuits for outputting an analog signal, corresponding to levels “?1” or “1”, and a low-pass filter for smoothing the analog signal output from the two unit analog circuits, as selected by codes output from the four-valued delta-sigma modulator. In case the input signal is ?2 or +2, outputs of the unit analog circuits are summed together to output an analog signal corresponding to ?2 or +2. In case the input signal is ?1 or +1, outputs of the unit analog circuits are alternately used to output an analog signal corresponding to ?1 or +1 to reduce the non-linearity error resulting from variations in the analog devices.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 9, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuya Matsumoto
  • Patent number: 6928369
    Abstract: The present invention provides a small, low power consumption ultrasonic flow velocity meter. The burst signal generation section 110 generates two kinds of burst signals with a phase difference and sends these burst signals to a pair of transmission/reception ultrasonic transducers 6 and 7 located on the upstream side and downstream side of the conduit to be measured 9. Upon reception of the corresponding burst signals, the pair of the transmission/reception ultrasonic transducers 6 and 7 convert the burst signals, send ultrasonic waves with a phase difference to the conduit to be measured 9, receive the ultrasonic wave sent by the other transmission/reception ultrasonic transducer and propagated through the conduit to be measured and convert the ultrasonic waves to received signals.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: August 9, 2005
    Assignee: Tokimec, Inc.
    Inventors: Masao Kishimoto, Ryohei Motegi, Yukihiko Suzuki, Hiroshi Iwabuchi
  • Patent number: 6925233
    Abstract: Interference filters which are optical components are erected in advance on optical paths in a transparent container, and the transparent container is filled with a photo-curable resin solution. Further, a jig is prepared for manufacturing an optical waveguide device. The jig includes a housing, and holes. On this occasion, positions of the holes are set such that light input through the hole reaches the holes via the interference filters. Optical fibers are fitted into the holes of the housing and the housing is mounted on the transparent container. Next, light at a predetermined wavelength is guided into the optical fibers so that optical waveguides are formed in the photo-curable resin solution. Next, the photo-curable resin solution is exchanged for a low-refractive-index photo-curable resin solution and then the low-refractive-index photo-curable resin solution is solidified wholly by ultraviolet light. Finally, for example, an optical fiber, a light-receiving element, etc. are provided.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: August 2, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yukitoshi Inui, Kuniyoshi Kondo, Manabu Kagami, Tatsuya Yamashita, Akari Kawasaki, Hiroshi Ito
  • Patent number: 6924515
    Abstract: The invention is to realize such a semiconductor light-emitting element which is higher in external quantum efficiency than an existing LED, and lower in production cost than an existing semiconductor laser. The light transmission insulating film is formed on a continuously incline face comprising the semiconductor layers having an opening angle etched in right angled V. The V shape incline is formed by a known technique, and both left and right inclined faces have the angle of 45°. Depending on the length of ? or the position of the light reflecting portion, probability that the light in duration of resonance is reflected may be made optimum or preferable. According to this structure, it is no longer necessary to carry out processing treatments of high degree, high precision, or high cost such as, e.g.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: August 2, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masanobu Senda, Jun Ito
  • Patent number: 6925100
    Abstract: In an LED, the area of contact between an ohmic electrode formed on a contact layer and the contact layer serves as an effective light-emitting area of a light-emitting layer. Therefore, while the area of contact between the ohmic electrode and the contact layer is kept small, a seat electrode is interposed so that the seat electrode is connected to a circuit wiring on a wiring board by a ball electrode being contact with the seat electrode at an area larger than the area. As a result, the size necessary for forming the ball electrode can be secured easily and the light-emitting area of the light-emitting layer in the LED can be reduced sufficiently. Accordingly, a capacitance component formed by clamping the light-emitting portion of the light-emitting layer can be reduced, so that a time constant at a leading edge of luminance and a time constant at a trailing edge of luminance can be reduced sufficiently to obtain a high speed.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 2, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masanobu Senda, Naoki Shibata
  • Patent number: 6924671
    Abstract: A general-purpose logic module is composed of: a first inverter 10 in which an input terminal is connected to a first node T1; a second node T2 connected to an output terminal of the first inverter; a second inverter 11 in which an input terminal is connected to a third node T3; a sixth node T6 connected to an output terminal of the second inverter; a third inverter 12 in which an input terminal is connected to a fourth node T4; a first transfer gate 20 in which an input terminal is connected to the output terminal of the first inverter, a first control input terminal is connected to the fourth node T4, and a second control input terminal is connected to an output terminal of the third inverter; a second transfer gate 21 in which an input terminal is connected to the output terminal of the second inverter, a first control input terminal is connected to the output terminal of the third inverter, and a second control input terminal is connected to the fourth node T4; and a fifth node T5 connected to an output t
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: August 2, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Masaharu Mizuno
  • Patent number: 6925460
    Abstract: The present invention relates to a method, system and computer program product for clustering data points and its application to text summarization, customer profiling for web personalization and product cataloging. The method for clustering data points with defined quantified relationships between them comprises the steps of obtaining lead value for each data point either by deriving from said quantified relationships or as given input, ranking each data point in a lead value sequence list in descending order of lead value, assigning the first data point in said lead value sequence list as the leader of the first cluster, and considering each subsequent data point in said lead value sequence list as a leader of a new cluster if its relationship with the leaders of each of the previous clusters is less than a defined threshold value or as a member of one or more clusters where its relationship with the cluster leader is more than or equal to said threshold value.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventors: Krishna Kummamuru, Raghuram Krishnapuram, Pradeep Kumar Dubey
  • Patent number: 6924185
    Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventors: David K. Anderson, Tien-Jen Cheng, Timothy J. Dalton, Christopher V. Jahnes, Andrew Lu, Chandrasekhar Narayan, Kevin S. Petrarca, Richard P. Volant, George F. Walker
  • Patent number: 6925589
    Abstract: A structure and method for translating address buffer coordinates for a device under test having two or more similar repeatable units. The method comprises identifying a repeatable unit of the repeatable units, preparing a look up table for translating buffer coordinates of a reference unit of the repeatable units and displacing information from the look up table to correspond to the repeatable units.
    Type: Grant
    Filed: January 21, 2000
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventor: Daniel Ben-Ezri
  • Patent number: 6924079
    Abstract: The present invention relates to a resist resin having an acid-decomposable group, which gives rise to decomposition of the acid-decomposable group to show an increased solubility to an aqueous alkali solution by the action of an acid, wherein the resist resin has, in the main chain, an alicyclic lactone structure represented by the following general formula (1). According to the present invention, a positive-type chemically amplified resist can be obtained which has high transparency to a far-ultraviolet light having a wavelength of about 220 nm or less, excellent etching resistance, and excellent adhesion to substrate; and a fine pattern required in production of semiconductor device can be formed. (wherein Z is an alicyclic hydrocarbon group having a lactone structure).
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: August 2, 2005
    Assignee: NEC Corporation
    Inventors: Katsumi Maeda, Shigeyuki Iwasa, Kaichiro Nakano, Etsuo Hasegawa
  • Patent number: 6924661
    Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, John M. Cohn, Kevin M. Grosselfinger, Susan K. Lichtensteiger, William F. Smith
  • Patent number: 6922510
    Abstract: An optical device includes at least one kind of and a plurality of optical circuits optically connected in series wherein the optical circuits are arranged in a spiral on a common substrate.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: July 26, 2005
    Assignee: NEC Corporation
    Inventor: Takaaki Hatanaka
  • Patent number: 6921009
    Abstract: A nailing machine, in which a part constituting a nose is changed so as to increase the service life of a driver blade for driving a nail. The nailing machine includes a nose having a nose hole in which the nail is supplied, and the driver blade made of metal. At least a part of a surface of the nose hole to be in contact with a front surface of the driver blade is provided with a protective body. The protective body is made of an organic material or a composite material of an organic material and a metal material. Due to this, direct mutual contact of the metal parts is prevented.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: July 26, 2005
    Assignee: Hitachi Koki Co., Ltd.
    Inventors: Satsuo Sato, Takuhiro Murakami, Kunio Yamamoto
  • Patent number: 6921923
    Abstract: An InGaN layer is formed on an undercoat layer of the same composition as the InGaN layer. The composition of the undercoat layer may be changed continuously or stepwise.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: July 26, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Naoki Shibata
  • Patent number: 6922349
    Abstract: A method and structure for a read only memory (ROM) cell array has the first drain of a first transistor connected to a true bitline and a second drain of a second transistor connected to a complement bitline. The first transistor also includes a first source, and the second transistor includes a second source. The connection of the first source or the second source to ground programs the ROM cell. With the invention, only the first source or the second source is connected to the ground and the other is insulated from electrical connections. Further, the connection of the source to ground comprises an electrical connection formed during manufacturing of the first transistor and the second transistor.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Barry, Peter F. Croce, Steven M. Eustis, Yabin Wang
  • Patent number: 6922617
    Abstract: An estimating unit 7 estimates an element aij of a system matrix based on state quantity including at least a longitudinal force Fx applied to a wheel, a vertical force Fz applied to the wheel and a vehicle speed V. A setting unit 8 sets a target value aij? regarding the element aij of the system matrix. A processing unit 9 calculates a control value so that the estimated element aij approaches the set target value aij?. Controlling units 10 to 13 control a vehicle based on the calculated control value. Here, the element aij is expressed by a sum of a linear term changing with linearity of the wheel and a nonlinear term changing with nonlinearity of the wheel, and the setting unit 8 sets the linear term of the element aij as the target value aij?.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: July 26, 2005
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Masaru Kogure, Koji Matsuno
  • Patent number: 6922433
    Abstract: To provide a CDMA demodulation circuit and a CDMA demodulation method capable of maintaining good receiving characteristics even in a mobile communication environment. A fading pitch estimation portion estimates a time at which a level of a received input signal drops due to fading by monitoring fluctuation in the level provided by a rake combining portion. Before the level drops, a finger path assignment control portion controls assignment of path timing to a fingers portion performed by a finger path assignment portion.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: July 26, 2005
    Assignee: NEC Corporation
    Inventor: Koichi Tamura
  • Patent number: 6921978
    Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
  • Patent number: 6922706
    Abstract: A computer method for enhancing shelf-space management. The method includes the steps of providing a shelf-space-requirements database comprising a compendium of individual shelf-space-requirements history; providing a shelf-space-availability database comprising a compendium of at least one of shelf-space management solutions, shelf-space information, and shelf-space diagnostics; and, employing a data mining technique for interrogating the shelf-space-requirements and shelf-space-availability databases for generating an output data stream, the output data stream correlating shelf-space-requirements problem with shelf-space-availability solution.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: July 26, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jerome M. Kurtzberg, Menachem Levanoni
  • Patent number: 6920261
    Abstract: According to the cross phase modulation suppressing device of the present invention, the wavelength multiplexing optical signal from an optical fiber having polarization orthogonality between the adjacent channels is split for every channel and the split optical signals are led to delaying optical waveguides of different lengths by the AWG (Arrayed Waveguide Grating) connected to a second port of an optical circulator, and the split optical signals with each delay added are reflected by the Farraday mirrors in polarization states orthogonal to each other and again led to the delaying optical waveguides. The reflected lights are combined by the AWG and supplied to a third port of the optical circulator as the wavelength multiplexing optical signal with orthogonality of polarization states kept between the adjacent channels.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: July 19, 2005
    Assignee: NEC Corporation
    Inventors: Yoshihisa Inada, Toshiharu Ito