Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8086188
    Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.
    Type: Grant
    Filed: June 8, 2008
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Tanaka, Hiroshi Kamizuma, Koji Maeda, Sungwoo Cha, Yukinori Akamine, Taizo Yamawaki
  • Patent number: 8086889
    Abstract: A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: December 27, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Ito, Yasuhiro Fujimura, Koki Tsutsumida, Shigeru Nakahara
  • Patent number: 8084373
    Abstract: A manufacturing method of a semiconductor device is provided which can uniformly form a good and thin silicon oxide film or the like at a relatively low temperature. In step 1, a semiconductor substrate is exposed to monosilane (SiH4). Then, in step 2, the remaining monosilane (SiH4) is emitted. In step 3, the semiconductor substrate is exposed to nitrous oxide plasma. A desired silicon oxide film is formed by repeating one cycle including steps 1 to 3 until a necessary thickness of the film is obtained.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsunori Murata, Yoshihiro Miyagawa
  • Patent number: 8081390
    Abstract: A variable magnification optical system ZL has, in order from the object side, a first lens unit G1 with a positive refractive power, a second lens unit G2 with a negative refractive power, a third lens unit G3 with a positive refractive power, a fourth lens unit G4, and a fifth lens unit G5 with a positive refractive power, and is configured to satisfy conditions of the following expressions: 2.49<|f4|/f5<4.69; and ?0.05??5w<0.085, where f4 is a focal length of the fourth lens unit, f5 is a focal length of the fifth lens unit, and ?5w is a lateral magnification of the fifth lens unit in the wide-angle end state.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: December 20, 2011
    Assignee: Nikon Corporation
    Inventor: Satoshi Hayakawa
  • Patent number: 8082398
    Abstract: There is a need for providing a data processor capable of easily prefetching data from a wide range. A central processing unit is capable of performing a specified instruction that adds an offset to a value of a register to generate an effective address for data. This register can be assigned an intended value in accordance with execution of an instruction. A buffer maintains part of instruction streams and data streams stored in memory. The buffer includes cache memories for storing the instruction stream and the data stream. From the memory, the buffer prefetches a data stream containing data corresponding to an effective address designated by the specified instruction stored in the cache memory. A data prefetch operation is easy because a data stream is prefetched by finding the specified instruction from the fetched instruction stream. Data can be prefetched from a wider range than the use of a PC-relative load instruction.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: December 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Yamada, Naoki Kato, Kesami Hagiwara
  • Patent number: 8079910
    Abstract: The present invention relates generally to a system and method for reviewing and evaluating performance. In particular, the present invention relates to a system and method for reviewing and evaluating performances of an official or group of officials at an event or events. Even more specifically, according to embodiments of the present invention, the system and method can involve reviewing and evaluating a referee's performance during a football game or games.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: December 20, 2011
    Inventor: Russell Acree
  • Patent number: 8079606
    Abstract: A castor wheel assembly on the underside of a shopping trolley comprises a wheel mounted to a wheel mount and rotatable about its rotational axis. A locking device including an engagement element and an actuator element is operatively coupled to the wheel mount for releasably engaging a locking element of the wheel mount to restrict swivelling of the wheel about a swivel axis of the wheel mount. The wheel is freely rotatable about the swivel axis when reversely rotated. Reverse rotation of the wheel urges the actuator element into pressing engagement with the wheel, driving the coupling portion of the engagement element away from the periphery of the wheel for disengagement of the engagement element from the locking element. Engagement of the engagement element and the locking element is only effected when the wheel is forwardly rotated to reduce the pressing engagement.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: December 20, 2011
    Assignee: Inautec Pty Limited
    Inventors: Graham Dull, Clinton Anthony Dull, Mathew Keith Trainor
  • Patent number: 8076709
    Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
  • Patent number: 8076192
    Abstract: Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Taniguchi, Kazuyoshi Shiba
  • Patent number: 8076957
    Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Isoda
  • Patent number: 8075909
    Abstract: A bioactive agent delivery system comprising an optically transparent contact lens having dispersed therein (1) an ophthalmically bioactive agent capable of diffusion through the contact lens and into the post-lens tear film when placed on the eye and (2) associated with the bioactive agent, an ophthalmically compatible polymeric surfactant in an amount sufficient to slow the rate of migration of the bioactive agent through the contact lens.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: December 13, 2011
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Anuj Chauhan, Yash Kapoor
  • Patent number: 8077065
    Abstract: In AD conversion of a voltage under measurement, data continuity is ensured between the result of conversion after amplification by using an amplifier circuit and the result of direct conversion without using the amplifier circuit. In AD conversion operation using a DA converter circuit, an amplifier circuit, and an AD converter circuit under the direction of a control circuit, an analog signal output from the DA converter circuit is directly converted by the AD converter circuit, and also the analog signal is converted therein after amplified by the amplifier circuit with an expected gain of 2n (“n” represents a positive integer). Based on resultant data thus obtained, a gain of the amplifier circuit and an offset thereof are calculated.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimi Iso, Kakeru Kimura, Tadashi Matsushima, Yuji Shimizu
  • Patent number: 8076191
    Abstract: In processing memory cells for forming a nonvolatile memory in a semiconductor device, a second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Yamakoshi, Hideyuki Yashima, Shinichiro Abe, Yasuhiro Taniguchi
  • Patent number: 8075833
    Abstract: A method for forming a container includes receiving a parison, enclosing the parison with a mold that includes a cavity, and inflating the parison in said mold to form a blow molded container with a moveable region at the cavity. The method further includes repositioning the moveable region before filling the blow molded container.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: December 13, 2011
    Assignee: Graham Packaging Company L.P.
    Inventor: Paul Kelley
  • Patent number: 8071121
    Abstract: An ophthalmically bioactive agent delivery system comprising a contact lens having dispersed therein as an oil-in-water microemulsion, an ophthalmically bioactive agent encapsulated in the oil phase, the oil phase comprising a material from which the agent VAN diffuse into and migrate through the contact lens into the post-lens tear film when the contact lens is placed on the eye and wherein the microemulsion is stabilized by the presence of a surfactant with sufficient packing at the oil-water interface to attenuate the rate of diffusion into and migration of agent through the contact lens.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: December 6, 2011
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Anuj Chauhan, Derya Gulsen Onbilger, Yash Kapoor, Chi-Chung Li
  • Patent number: 8071399
    Abstract: An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. Measures are: obtaining an image of a region PCA within the surface of a wafer including a region OGA pressed by a pressing member, at the center of which a chip just after probe-tested is located, by an imaging means such as a camera; comparing an image of a normal chip obtained in advance and an image of all the chips within the region PCA; and judging thereby whether an abnormal shape is caused or not in all the chips within the region PCA.
    Type: Grant
    Filed: January 13, 2008
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masao Okayama
  • Patent number: 8073643
    Abstract: A semiconductor device which includes a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down, and an internal voltage determining circuit for determining the voltage of the internal power supply in which power is shut down. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When the power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, the increased voltage of the internal power supply is determined by the internal voltage determining circuit, operation of a circuit block is started, and the switch is turned on.
    Type: Grant
    Filed: May 18, 2008
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takayasu Ito, Mitsuru Hiraki, Masashi Horiguchi, Toyohiro Shimogawa
  • Patent number: 8074005
    Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hidemi Oyama, Masanobu Kawamura, Takuya Ikeguchi, Masanori Matsumoto, Hiroyuki Kawajiri
  • Patent number: 8072035
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda
  • Patent number: D651278
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: December 27, 2011
    Inventor: Gregory D. Graves