Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8068113
    Abstract: The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without significantly increasing the occupation area. A liquid crystal controller/driver in which a RAM for storing display data is provided in a chip and the storage capacity of the built-in RAM is determined according to the size of a display screen of a liquid crystal panel to be driven, includes a fuse circuit for setting a defect address, and a comparing circuit for comparing the defect address set in the fuse circuit with an input address. The liquid crystal controller/driver also has a redundant circuit, when the addresses match each other, for replacing the input address with an address that instructs the spare memory area and supplying the address to an address decoder.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: November 29, 2011
    Assignee: Renesas Electronic Corporation
    Inventors: Masaru Iizuka, Iori Shiraishi, Sosuke Tsuji, Hiroto Kinno
  • Patent number: 8067789
    Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: November 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shunsuke Toyoshima, Kazuo Tanaka, Masaru Iwabuchi
  • Patent number: 8068526
    Abstract: A purpose is to provide a semiconductor optical device having good characteristics to be formed on a semi-insulating InP substrate. Firstly, a semi-insulating substrate including a Ru—InP layer on a conductive substrate is used. Secondly, a semi-insulating substrate including a Ru—InP layer on a Ru—InP substrate or an Fe—InP substrate is used and semiconductor layers of an n-type semiconductor layer, a quantum-well layer, and a p-type semiconductor layer are stacked in this order.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 29, 2011
    Assignee: Opnext Japan, Inc.
    Inventors: Shigeki Makino, Takeshi Kitatani, Tomonobu Tsuchiya
  • Patent number: 8067807
    Abstract: In an LCD driver IC, a high-breakdown-voltage MISFET is mounted together with a typical low-breakdown-voltage MISFET. Because the high-breakdown-voltage MISFET has a gate oxide film thicker than that of the typical MISFET, the electrode of the high-breakdown-voltage MISFET is inevitably high in level. Accordingly, the depth of a gate contact is shallow so that process compatibility with the typical portion is necessary. In the present invention, in, e.g., the channel width direction of the high-breakdown-voltage MISFET, the boundary of a thick-film gate oxide region is located inwardly of the end of a gate electrode. At the gate electrode portion thus lowered in level, a gate contact is disposed so that the boundary of the thick film is located inwardly of the end of the gate electrode and between the gate contact and a channel end.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: November 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masatoshi Taya
  • Patent number: 8066921
    Abstract: A method of producing a container and a closure comprises blow molding a body comprising a container portion and a closure portion joined together, and separating the closure portion from the container portion. A container and/or a closure produced according to the method are also disclosed, as well as an intermediate product for producing a container and a closure.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: November 29, 2011
    Assignee: Graham Packaging Company, L.P.
    Inventors: Sheldon Yourist, David W. Cargile, Edward V. Perone
  • Patent number: 8063349
    Abstract: A solar heliostat and system are described with various characteristics particularly suitable for concentrating systems with a relatively large number of small heliostats. Other features contribute to high performance, low cost, high durability, and high temperature operation, such as desired for high efficiency thermal power generation.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: November 22, 2011
    Assignee: Brightsource Industries (Israel) Ltd.
    Inventors: Shmuel Huss, Hagai Huss, Israel Kroizer, Yoel Gilon, Danny Franck, Susan Walzer
  • Patent number: 8064261
    Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
  • Patent number: 8063478
    Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 8062802
    Abstract: A system and method are provided for exchanging heat in fuel cell systems (100) in which the anode and cathode off-gases are provided with separated flow paths. In one embodiment, where a fuel cell stack (110) has separate anode and cathode off-gas flow paths, separate anode off-gas from the at least one fuel cell stack (110) and at least one heat transfer fluid are passed through a first heat exchange element (126) to exchange heat between the anode off-gas and the heat transfer fluid. The cathode off-gas exiting the at least one fuel cell stack is then combined with the anode off-gas from the heat exchange element (126) in a burner and burned.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 22, 2011
    Assignee: Ceres Intellectual Property Company Limited
    Inventors: James Devriendt, Robert Morgan, Paul Barnard, Robert Leah
  • Patent number: 8063489
    Abstract: In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.).
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Patent number: 8060978
    Abstract: A road sweeper includes a blower housing having an opening, a hopper having an opening, and the openings being in axial alignment when the hopper and blower housing are each in a sweeping position thereof. The blower housing is biased for tilting movement from its sweeping position to an inclined dump position upon relative movement of the hopper to preclude abrasion, wear and damage to an O-ring seal disposed between the openings. The blower housing can also be moved to a third repair position in which components thereof are accessible from the cab side of the sweeper.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: November 22, 2011
    Assignee: TYMCO, Inc.
    Inventors: Gary B. Young, James C. Crow
  • Patent number: 8061895
    Abstract: There is provided a semiconductor device which can maintain a high tuning accuracy while suppressing a cost increase and suppress an increase in the time required for tuning. There are included, in addition to variable resistors configuring a level shift circuit, an additional resistor coupled between the output node of a VBGR voltage of a BGR circuit and one of the variable resistors and an additional resistor coupled between the other of the variable resistors and a reference voltage. N-channel MOS transistors are coupled in parallel with the additional resistors, respectively.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Masaki Tsukude
  • Patent number: 8063433
    Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Ishimaru, Yasuhiro Shimamoto, Toshiyuki Mine, Yasunobu Aoki, Koichi Toba, Kan Yasui
  • Patent number: 8062911
    Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
  • Patent number: 8063620
    Abstract: The present invention provides a switching power source and a semiconductor integrated circuit which realize an acquisition a sufficient driving voltage of a high-potential side switching element M1 even when a power source voltage VDD is low.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kyoichi Hosokawa, Ryotaro Kudo, Toshio Nagasawa, Koji Tateno
  • Patent number: 8060790
    Abstract: This invention is to provide a technology for taking out trace information externally without lacking under the condition of limited output bandwidth. A semiconductor integrated circuit provided includes: a processing unit which can perform arithmetic processing according to a predetermined program and can output trace information with respect to the arithmetic processing; and a trace compression unit which can compress the trace information outputted from the processing unit. The trace compression unit includes a storage device, a comparator unit which can compare trace information stored in the storage device and the trace information newly outputted from the processing unit, and a trace information compression controller which can compress trace information to be externally outputted, based on the comparison result of the comparator unit.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: November 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Jun Sakiyama, Naoki Kato
  • Patent number: 8053826
    Abstract: The charge retention characteristics of a non-volatile memory, particularly, a MONOS-type non-volatile memory is improved. In a non-volatile memory cell including a tunnel silicon oxide film (107), a silicon nitride film (104) serving as a charge storage film, a silicon oxide film (105), and a gate electrode (108) which are sequentially formed on a semiconductor substrate, the tunnel silicon oxide film (107) has a stacked structure of a silicon oxynitride film (102) and a silicon oxide film (103). Herein, it is configured such that a density of nitrogen atoms contained in the silicon oxynitride film (102) decreases as a distance from an interface with the semiconductor substrate increases in a film-thickness direction of the silicon oxynitride film (102).
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiki Yonamoto
  • Patent number: 8053893
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: November 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwaskai, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: D649366
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: November 29, 2011
    Assignee: Innovation U.S.A., Inc.
    Inventor: Per Weiss Andersen
  • Patent number: D649367
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: November 29, 2011
    Assignee: Innovation U.S.A., Inc.
    Inventor: Per Weiss Andersen