Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7911708
    Abstract: A zoom lens includes a first lens group having a positive refractive power, a second lens group having a negative refractive power, a third lens group having a positive refractive power, and a fourth lens group having a positive refractive power, which are disposed in order from an object along the optical axis, wherein the third lens group comprises: a pre-group, which has a first positive lens, a negative meniscus lens having a convex surface facing the object, a second positive lens, and which has a positive refractive power; and a negative meniscus lens having a convex surface facing the object, which are disposed in order from the object; at least one of three surfaces of an object side and image side lens surfaces of the first positive lens and an object side lens surface of the negative meniscus lens is aspherical; and at least one of three surfaces of an object side lens surface of the second positive lens, and an object side and image side lens surfaces of the negative meniscus lens is aspherical.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: March 22, 2011
    Assignee: Nikon Corporation
    Inventor: Susumu Sato
  • Patent number: 7911706
    Abstract: In a zoom lens having a plurality of lens groups which are disposed in that order from an object, a first lens group that is disposed to closest to the object among the plurality of lens groups has positive refractive power and comprises a light path bending element which bends the path of light and a plurality of lens components which are disposed closer to the object than the light path bending element; and, where the distance on the optical axis from the surface closest to the object in the first lens group to the surface closest to the object in the light path bending element is L1 and the distance on the optical axis of the light path bending element is Lp, the conditional expression L1/Lp<1.0 is satisfied.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: March 22, 2011
    Assignee: Nikon Corporation
    Inventor: Toshinori Take
  • Patent number: 7912481
    Abstract: An invention for estimating the first path of an arrival signal by a method and device with a simple structure and lower power consumption. In this method, the nominal pulse repetition frequency or its integer multiple are A/D converted at a frequency less than the multiplicative inverse of the pulse width, the AD conversion timing is offset by time resolution ?t and the receive signal measured, data stored in a RAM, and the first path output time is estimated based on sequentially rearranging of the stored waveform data.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: March 22, 2011
    Assignee: Hitachi Ltd.
    Inventors: Ryosuke Fujiwara, Kenichi Mizugaki, Masayuki Miyazaki
  • Patent number: 7911851
    Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 22, 2011
    Assignee: BTG International Inc.
    Inventor: Gerald J. Banks
  • Patent number: 7909399
    Abstract: An orthopedic back support for displacing a person's weight from the lower area of the spine by providing support for the upper torso and for use with a chair or seat having a seat base and a seat back. A flexible fabric cross piece is connected between vertical axillary support members to provide back support. The cross piece may include vertical channels or sleeves at opposite sides to receive and support the vertical members. The entire unit is portable and when in use facilitates unobtrusive intermittent use and easy ingress and egress from the seat to relieve discomfort after long periods of use. A rib band may be attached to the flexible fabric by means of hook and loop fabric strips such as Velcro to form a detachable connection. A hook strip is disposed on the back of the rib band and is adapted to cooperate with a mating soft loop strip on the forward side of the flexible fabric member which supports the user in a seated position by the combined action of the flexible fabric and rib band.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: March 22, 2011
    Inventor: John G. Rutty
  • Patent number: 7911299
    Abstract: A microactuator has a fixed portion and a movable portion that is provided in such a way as to be movable relative to the fixed portion between a first position at which it is in contact with a predetermined portion of the fixed portion and a second position away from the first position. The fixed portion has a first electrode portion, the movable portion has a second electrode portion that can produce an electrostatic force between it and the first electrode portion by a voltage between it and the first electrode portion, and the first and second electrode portions are arranged in such a way that a first force that biases the movable portion in a direction toward the first position according to the electrostatic force created when the voltage is constant reaches a peak when the movable portion is at a third position between the first position and the second position.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: March 22, 2011
    Assignee: Nikon Corporation
    Inventor: Junji Suzuki
  • Patent number: 7910990
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: March 22, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 7909151
    Abstract: The present invention provides a lock-up clutch mechanism for a torque converter, comprising a lock-up piston and a front cover having an engagement surface capable of being engaged with the lock-up piston and in which a friction material is stuck to wither one of the lock-up piston and the front cover and in which engagement and disengagement are performed in accordance with a hydraulic pressure difference between the front cover and the lock-up piston and wherein the friction material includes a first flat friction surface disposed at an outer diameter side and a second tapered friction surface disposed at an inner diameter side and further wherein, when the lock-up piston and the front cover are slip-controlled, the first friction surface is engaged with uniform face pressure, and, when the lock-up piston and the front cover are substantially integrally joined with a great hydraulic pressure difference under slip control, maximum face pressure is generated at a border between the first friction surface and
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 22, 2011
    Assignee: NSK-Warner K.K.
    Inventors: Hideki Matsumoto, Hideaki Takabayashi, Chisato Yagi
  • Patent number: 7911221
    Abstract: A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data, and a second flip flop that stores the second data. Furthermore, the speed performance measurement circuit includes a first comparator circuit that compares output of the first flip flop to output of the second flip flop, and a third flip flop that stores output data from the first comparator circuit in accordance with timing of the first clock signal. Data in a normal path is compared to data in a path delayed by a certain time to measure speed, and power voltage of a circuit is determined based on such comparison. Thus, change in speed with respect to power voltage in a critical path can be measured.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: March 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Kenichi Osada
  • Patent number: 7912698
    Abstract: The invention relates to a method for automatically analyzing data and constructing data classification models based on the data. In an embodiment of the method, the method includes selecting a best combination of methods from a plurality of classification, predictor selection, and data preparatory methods; and determining a best model that corresponds to one or more best parameters of the classification, predictor selection, and data preparatory methods for the data to be analyzed. The best model; and returning a small set of predictors sufficient for the classification task.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: March 22, 2011
    Inventors: Alexander Statnikov, Constantin F. Aliferis, Ioannis Tsamardinos, Nafeh Fananapazir
  • Patent number: 7905319
    Abstract: A venturi muffler is made of a plurality of metallic tubular stepped members which are stacked together and define at least one sound-reflective chamber which opens through an annular venturi passage into an axial flow passage of the venturi muffler thereby creating a partial vacuum in the annular chamber. The annular chambers include aligned openings through which exhaust gasses flow but are also reflected by walls of the sound-reflective chambers. Therefore, the exhaust sound or noise is dampened by the cancellation of sound waves 180 degrees out of phase with each other, the creation of a partial vacuum through which sound cannot propagate or propagates minimally, and by the heat removed by all of the metallic heat-conductive venturi-forming segments of the venturi muffler.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: March 15, 2011
    Inventor: John T. Sullivan
  • Patent number: 7908204
    Abstract: A securities analysis tool and method that allows a user to quickly and easily identify securities or stocks with the highest speed change per unit time and acceleration, or rate of change of speed, relative to other securities or stocks. More specifically, a human-machine interface includes speed and acceleration indicators that allow a user to visualize for one or more securities: the price speed, which is the percentage change per unit time; the price acceleration, which is the rate of change of price speed; the accumulation speed, which is the percentage change per time unit greater than zero; the accumulation acceleration, which is the rate of change of accumulation speed; the distribution speed, which is the percentage change per unit time less than zero; and the distribution acceleration, which is the rate of change of accumulation speed.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 15, 2011
    Inventor: Yuri Boglaev
  • Patent number: 7907435
    Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: March 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
  • Patent number: 7907354
    Abstract: A zoom lens comprises the following lens groups in the order from an object side: a first lens group having a positive refracting power; a second lens group having a negative refracting power; a third lens group having a positive refracting power; and a fourth lens group having a positive refracting power; wherein, upon zooming, at least the first lens group and the fourth lens group move to the object side; and wherein the third lens group comprises a negative meniscus lens with a convex surface on an image side and with both side faces thereof being exposed to air, which is located nearest to the image side.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: March 15, 2011
    Assignee: Nikon Corporation
    Inventor: Toshinori Take
  • Patent number: 7908424
    Abstract: A controller 3 of a memory card is a provided with a command decoding circuit 6 for decoding commands issued by a host HT, a command enable register 8 in which the validity or invalidity of the received command, and a command detection signal generating circuit 7 for detecting a valid command on the basis of the result of decoding by the command decoding circuit 6 and a value set by the command enable register 8. If the command enable register 8 receives a validly set command, the command detection signal generating circuit 7 will supply a detection signal to a control unit 4 to execute processing prescribed for each command. the command enable register 8 receives an invalidly set command, no detection signal will be supplied, and the command will be ignored.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: March 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Shikata, Kunihiro Katayama, Masato Matsumoto, Kazuto Izawa, Motoki Kanamori
  • Patent number: 7907442
    Abstract: In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN3 and MN4) and capacitively coupled to the input nodes of the data latch circuit via gates of first MOS transistors (MP1 and MP2) respectively. In this separated state, the first and second signal lines and the input nodes of the data latch circuit are precharged to different voltages, so that the gate-to-source and drain-to-source voltages of the first MOS transistors are controlled by the voltages of the first and second signal lines respectively.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: March 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Naoki Kitai, Satoru Hanzawa, Akira Kotabe
  • Patent number: 7906796
    Abstract: In a bipolar device, such as transistor or a thyristor, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides, among other things, an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 15, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Hidekatsu Onose, Natsuki Yokoyama
  • Patent number: 7907350
    Abstract: Providing a high optical performance zoom lens system with realizing a high zoom ratio and compactness suitable for a highly integrated electronic imaging device. The system includes, in order from an object along an optical axis: a first group G1 having positive refractive power; a second group G2 having negative refractive power; a third group G3 having positive refractive power; a fourth group G4 having positive refractive power; and a fifth group G5 having negative refractive power. Upon zooming from a wide-angle end state W to a telephoto end state T, the second group G2 and the fourth group G4 are moved along the optical axis. The first group G1 includes, in order from the object along the optical axis, a front group G1f having negative refractive power, an optical-path-bending element P for bending an optical path, and a rear group G1r having positive refractive power. Given expression is satisfied.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: March 15, 2011
    Assignee: Nikon Corporation
    Inventor: Shinichi Mitsuki
  • Patent number: 7903013
    Abstract: Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: March 8, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kenichiro Yamaguchi, Atsushi Okumura, Mitsugu Kusunoki, Tomoo Murata
  • Patent number: D634647
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: March 22, 2011
    Assignee: Fischbach KG Kunststoff-Technik
    Inventor: Achim Helmenstein