Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8278169
    Abstract: The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Takashi Hashimoto, Kosuke Okuyama
  • Patent number: 8275325
    Abstract: The transmitter of the transceiver includes: a transmitter-side mixers of a transmitter-side modulator; a transmitter-side voltage-controlled oscillator; and a transmitter-side divider. The divider having a dividing factor of a non-integral number is supplied with an oscillating output of the oscillator. A pair of non-quadrature local signals having a phase difference of 90° plus a predetermined offset angle is produced by the divider and supplied to the mixers. The transmitter includes a phase-shift unit which converts a pair of quadrature transmit signals having a phase difference of about 90° on an analog basis into a pair of non-quadrature shifted transmit signals. Consequently, quadrature modulation is performed by the mixers. Use of a similar configuration enables the reduction in interference of an RF signal with local signals supplied to receiver-side mixers of the receiver.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: September 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Tanaka, Hiroshi Kamizuma, Koji Maeda, Sungwoo Cha, Yukinori Akamine, Taizo Yamawaki
  • Patent number: 8274157
    Abstract: A semiconductor device having redistribution interconnects in the WPP technology and improved reliability, wherein the redistribution interconnects have first patterns and second patterns which are electrically separated from each other within the plane of the semiconductor substrate, the first patterns electrically coupled to the multi-layer interconnects and the floating second patterns are coexistent within the plane of the semiconductor substrate, and the occupation ratio of the total of the first patterns and the second patterns within the plane of the semiconductor substrate, that is, the occupation ratio of the redistribution interconnects is 35 to 60%.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: September 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yuki Koide, Masataka Minami
  • Patent number: 8273366
    Abstract: A drug delivery system comprising a contact lens having dispersed therein as nanoparticles having a particle size less than about 200 nm, an ophthalmic drug nanoencapsulated in a material from which said ophthalmic drug is capable of diffusion into and migration through said contact lens and into the post-lens tear film when said contact lens is placed on the eye.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: September 25, 2012
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Anuj Chauhan, Derya Gulsen
  • Patent number: 8270230
    Abstract: The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Kenichi Osada
  • Patent number: 8268682
    Abstract: When a natural oxide film is left at the interface between a metal silicide layer and a silicon nitride film, in various heating steps (steps involving heating of a semiconductor substrate, such as various insulation film and conductive film deposition steps) after deposition of the silicon nitride film, the metal silicide layer partially abnormally grows due to oxygen of the natural oxide film occurring on the metal silicide layer surface. A substantially non-bias (including low bias) plasma treatment is performed in a gas atmosphere containing an inert gas as a main component on the top surface of a metal silicide film of nickel silicide or the like over source/drain of a field-effect transistor forming an integrated circuit. Then, a silicon nitride film serving as an etching stop film of a contact process is deposited. As a result, without causing undesirable cutting of the metal silicide film, the natural oxide film over the top surface of the metal silicide film can be removed.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takuya Futase, Shuhei Murata, Takeshi Hayashi
  • Patent number: 8268285
    Abstract: A process and method for recovering elemental tellurium from minerals and acidic solutions using a reducing sugar as the reducing agent in order to reduce and precipitate tellurium as tellurium dioxide (TeO2) from which elemental tellurium may be recovered.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: September 18, 2012
    Assignee: Pacific Rare Specialty Metals and Chemicals, Inc.
    Inventors: Robert John Hisshion, Crispinne C. Patiño
  • Patent number: 8271157
    Abstract: A steering mechanism is provided on an equilateral triangular base of a mobile mechanism, and three joints are attached to the base at the three vertexes thereof. Links are attached to the three joints respectively. On each link is provided a steering mechanism. The equilateral triangular base of the mobile mechanism is moved or rotated by periodically driving the three joints while steering the four steering mechanisms.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: September 18, 2012
    Inventor: Hiroaki Yamaguchi
  • Patent number: 8269266
    Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Takashi Hashimoto
  • Patent number: 8269309
    Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: September 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara, Taichi Hayamizu, Yuichi Kawano
  • Patent number: 8266450
    Abstract: It is possible to achieve the protection of software with reduced overhead. For example, a memory for storing an encrypted code prepared in advance and a decryptor module for decrypting the code are provided. The decryptor module includes, for example, a three-stage pipeline and a selector for selecting one output from the outputs of each stage of the pipeline. When a branch instruction is issued and subsequent inputs of the pipeline are in the order of CD?1, CD?2, . . . , the decryptor module outputs a first decrypted code by performing a one-stage pipeline process to CD?1. Next, the decryptor module outputs a second decrypted code by performing a two-stage pipeline process to CD?2, and the decryptor module outputs a third decrypted code by performing a three-stage pipeline process to CD?3 (and subsequent codes). Therefore, in particular, the overhead to CD?1 can be reduced.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: September 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Endo, Toshio Okochi, Shunsuke Ota, Tatsuya Kameyama
  • Patent number: 8264771
    Abstract: A tripod-connecting adapter for connecting a pair of binoculars to a tripod comprising: a base portion that has a width in which a left and a right lens barrels of the pair of binoculars to be placed thereon come into contact therewith, and restricts rotation of the pair of binoculars around a joint shaft that connects the pair of lens barrels of the pair of binoculars; and a holding device that is provided on the base portion and is connected to the joint shaft to support the pair of lens barrels so that said pair of lens barrels may be placed on an upper surface of the base portion to come in contact therewith, and restricts movement of the pair of binoculars in an optical axis direction of the pair of binoculars.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: September 11, 2012
    Assignee: Nikon Vision Co., Ltd.
    Inventor: Mitsuo Yamamoto
  • Patent number: 8264893
    Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 11, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
  • Patent number: 8258561
    Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
  • Patent number: 8257593
    Abstract: A device, system and method for exchanging components between first and second fluids by direct contact in a microfluidic channel. The fluids flow as thin layers in the channel. One of the fluids is passed through a filter upon exiting the channel and is recycled through a secondary processor which changes the fluid's properties. The recycled fluid is reused for further exchange. The filter excludes blood cells from the recycled fluid and prevents or limits clogging of the filter. The secondary processor removes metabolic waste and water by diafiltration.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 4, 2012
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Edward F. Leonard, Alan C. West, Christian Paul Aucoin, Edgar E. Nanne
  • Patent number: 8256132
    Abstract: A silent hair dryer and a silencer for a hair dryer includes at least one casing with an inlet end and an outlet end and enclosing at least one turbine sucking in air via at least one admission orifice upstream of the turbine and expelling it downstream via at least one outlet orifice. The silent hair dryer includes at least one chamber upstream of the admission orifice and an inlet orifice for aspiration of air upstream of the chamber; the diameter of the chamber being greater than the diameter of the admission orifice and the diameter of the inlet orifice, the length and the diameter of the chamber being of such a size so as to define a volume turned as a function of the sound frequencies to be attenuated by the silencer.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: September 4, 2012
    Assignee: Velecta Paramount
    Inventors: Christophe Gaillard, Michel Guillosson, Roland Quessard
  • Patent number: 8258700
    Abstract: A plasma display panel has a front substrate (3) and a back substrate (2) arranged opposed to each other through a discharge space (4). On the back substrate, a fluorescent layer (5) is formed. On the front substrate, display electrodes are formed extending in a horizontal direction, a discharge cell area is demarcated corresponding to the display electrodes, and a plurality of shielding films (13) extending in the horizontal direction are moreover formed at each position which is among the display electrodes and within the discharge cell area. When the distance between the shielding films and the fluorescent layer is set to be D, the width L of a shielding film and the distance S between the shielding films satisfy 0.58?L?D and D?S?1.73D. This reduces the reflectance ratio of outdoor daylight to improve lighted room contrast.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: September 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Akira Otsuka, Takashi Sasaki
  • Patent number: 8258604
    Abstract: To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device. A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Bando, Kazuyuki Misumi, Tatsuhiko Akiyama, Naoki Izumi, Akira Yamazaki
  • Patent number: 8259400
    Abstract: A zoom lens system including, in order from an object, a first lens group G1 having negative refractive power, a second lens group G2 having positive refractive power, a third lens group G3 having negative refractive power, and a fourth lens group G4 having positive refractive power, upon zooming from a wide-angle end state W to a telephoto end state T, varying respective distances between adjacent lens groups G1, G2, G3, G4, shifting at least one portion of the third lens group G3 in a direction including a component perpendicular to the optical axis, and satisfying given conditional expressions, thereby providing a zoom lens system having a lens capable of moving in a direction including a component perpendicular to the optical axis, and realizing a high zoom ratio and excellent optical performance.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: September 4, 2012
    Assignee: Nikon Corporation
    Inventor: Satoru Shibata
  • Patent number: 8259524
    Abstract: The present invention is directed to provide a semiconductor device having a dual-port memory circuit in which influence of placement of replica cells exerted on enlargement of chip area is reduced. A memory cell array of a dual-port memory circuit has: a first replica cell array used to respond to an instruction of reading operation from one of dual ports; and a second replica cell array used to respond to an instruction of reading operation from the other dual port. Each of the replica cell arrays has: replica bit lines obtained by mutually short-circuiting parallel lines having a length obtained by cutting, in half, an inversion bit line and a non-inversion bit line of complementary bit lines to which data input/output terminals of a memory cell are coupled; and replica cells coupled to the replica bit lines and having transistor placement equivalent to that of the memory cells.
    Type: Grant
    Filed: July 18, 2010
    Date of Patent: September 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyotada Funane, Yuta Yanagitani, Shinji Tanaka