Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7752526
    Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
  • Patent number: 7751255
    Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
  • Patent number: 7750464
    Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Yoshikawa, Motoo Suwa, Kazuyuki Sakata
  • Patent number: 7750427
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Patent number: 7745288
    Abstract: A semiconductor device having a non-volatile memory is disclosed, whose disturb defect can be diminished or prevented. A memory cell of the non-volatile memory has a memory gate electrode formed over a main surface of a semiconductor substrate through an insulating film for charge storage. A first side wall is formed on a side face of the memory gate electrode, and at a side face of the first side wall, a second side wall is formed. On an upper surface of an n+-type semiconductor region for source in the memory cell there is formed a silicide layer whose end portion on the memory gate electrode MG side is defined by the second side wall.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: June 29, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Satoru Machida, Munekatsu Nakagawa, Kentaro Saito, Toshikazu Matsui, Takashi Hashimoto, Kosuke Okuyama
  • Patent number: 7743673
    Abstract: A power wrench (10) for turning a screw is supplied by a hydraulic unit (25) that contains a positive displacement pump (26) and supplies a defined rate of flow. The pressure in a hydraulic pressure line (28) is measured by a pressure sensor (32) and provided to a control unit (31). The volume flow of the hydraulic unit (25) is determined in amount per unit of time. The piston stroke per unit of time can be determined due to the fact that the filling volume of the hydraulic cylinder is known. The piston acts upon a lever system that turns the moving part. The turning angle per unit of time can be determined due to the fact that the lever length is known. This makes it possible to dispense with an angle measuring device and to determine the turning angle merely by measuring pressure.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: June 29, 2010
    Assignee: Wagner Vermögensverwaltungs-GmbH & Co. KG
    Inventors: Paul-Heinz Wagner, Ulf Sittig, Guenter Andres, Bernd Thelen
  • Patent number: 7746253
    Abstract: The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (?) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: June 29, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Akira Kitagawa, Akihiro Kitagawa
  • Patent number: 7746453
    Abstract: A pattern defect inspection apparatus capable of detecting minute defects on a sample with high sensitivity without generating speckle noise in signals is realized. Substantially the same region on a surface of a wafer is detected by using two detectors at mutually different timings. Output signals from the two detectors are summed and averaged to eliminate noise. Since a large number of rays of illumination light are not simultaneously irradiated to the same region on the wafer, a pattern defect inspection apparatus capable of suppressing noise resulting from interference of a large number of rays, eliminating noise owing to other causes and detecting with high sensitivity minute defects on the sample without the occurrence of speckle noise in the signal can be accomplished.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: June 29, 2010
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hidetoshi Nishiyama, Kei Shimura, Sachio Uto, Minori Noguchi
  • Patent number: 7743278
    Abstract: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: June 22, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yuri Ikeda, Yoshikazu Aoto, Jun Matsushima, Hiroyuki Sasaki, Tomoyoshi Ujii, Makoto Saen
  • Patent number: 7741677
    Abstract: After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: June 22, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Sakai, Atsushi Hiraiwa, Satoshi Yamamoto
  • Patent number: 7742227
    Abstract: Providing a microscope apparatus including an optical mount member capable of supporting various optical devices even without a large amount of space. A base body 10 arranged on a mount surface 9a of a vibration isolation table 9 is provided substantially perpendicularly to the mount surface 9a. A plurality of rails 32 through 36 are provided on the base body 31 vertically to the mount surface 9a so as to provide a plurality of extension optical devices such as a Galvanic scanner 64 to be combined with the microscope main body 10.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: June 22, 2010
    Assignee: Nikon Corporation
    Inventor: Takashi Kawahito
  • Patent number: 7740118
    Abstract: The present invention provides, a roller-type one-way clutch comprising an annular outer race provided at its inner periphery with a cam surface, an inner race spaced apart from the outer race in a radially inner diameter side and disposed in coaxial with the outer race for a relative movement therewith and having an annular outer peripheral track surface, a plurality of rollers disposed between the outer race and the inner race and adapted to transmit torque between the outer peripheral track surface and the cam surface, a cage for holding the plurality of rollers, and a C-shaped annular spring for biasing the rollers toward a direction in which the rollers are engaged by the cam surface, through the cage, and wherein the C-shaped annular spring is assembled in a diameter-enlarged condition.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: June 22, 2010
    Assignee: NSK-Warner K.K.
    Inventors: Hirobumi Shirataki, Kazuhiko Muramatsu
  • Patent number: 7735304
    Abstract: A system for processing a simplified plastic container (C) that is to be filled with a hot product includes the step of blow-molding parison to form a container body, where the container body has a neck, a base, a side surface relatively free of structural geometry that surrounds an interior of the container body and, prior to being filled with the hot product, a projection (12) extending from the container body. After the container body is filled with a hot product in a production line, the neck of the filled container body is capped with a cap and then, the container body is cooled. During the cooling operation, the hot product is contracted so that the projection extending from the container can be pushed (P) into the container body like a traditional push-up so that the resultant, filled and cooled container body is relatively free of structural geometry.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: June 15, 2010
    Inventors: Paul Kelley, Kent Goss, Philip Sheets, Ted Lyon, Charles A. Ryl-Kuchar
  • Patent number: 7737792
    Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 15, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kawamoto, Masaru Kokubo
  • Patent number: 7738181
    Abstract: Providing a compact zoom lens exhibiting optical performance, of which a chromatic aberration in a telephoto state is well corrected. The zoom lens includes a plurality of lens groups, the plurality of lens groups includes at least three lens groups with positive refractive power, each of the three lens groups with positive refractive power has a positive lens, and given conditional expressions are satisfied.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: June 15, 2010
    Assignee: Nikon Corporation
    Inventor: Susumu Sato
  • Patent number: 7736985
    Abstract: The performance of a sensor in a semiconductor device can be improved. A plurality of oscillators forming an ultrasonic sensor are arranged on a main surface of a semiconductor chip. A negative-type photosensitive insulating film which protects the oscillators is deposited on an uppermost layer of the semiconductor chip. At the time of exposure for forming an opening in the photosensitive insulating film, the semiconductor chip is divided into a plurality of exposure areas and exposed, and then, the exposure areas are jointed so that the entire area is exposed. At this time, a stitching exposure area is arranged so that a center of the stitching exposure area in a width direction in the joint portion of the adjacent exposure areas is positioned at a center of a line which connects centers of oscillators located above and below the stitching exposure area.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: June 15, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Enomoto, Katsuya Hayano, Shuntaro Machida
  • Patent number: 7736272
    Abstract: A system and method for providing visual feedback to a user of an exercise machine for gauging fitness progress of the user. The system provides a user of an exercise machine with a virtual competition in which the user competes against virtual competitors based on his past performances or those of other users, either as an individual or as a member of a team. The team may also be part of a league. For an individual competing against his own past performance(s), the system may raise the level of performance required to win the virtual competition, and may also lower the level of performance required if the user is not performing well on a particular day. For an individual competing against others in either real-time or against designated results, either as part of a team or a league, the system may reduce the isolation, disconnection, and tedium often experienced by users of cardiovascular exercise equipment and provide a social outlet.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: June 15, 2010
    Assignee: Pantometrics, Ltd.
    Inventor: Mark H. Martens
  • Patent number: 7732261
    Abstract: In a memory cell array on a main surface of a semiconductor substrate, a floating gate electrode for accumulating charges for information is arranged. The floating gate electrode is covered with a cap insulating film and a pattern of a first insulating film formed thereon. Further, over the entire main surface of the semiconductor substrate, a second insulating film is deposited so that it covers the pattern of the first insulating film and a gate electrode. The second insulating film is formed by a silicon nitride film formed by a plasma CVD method. The first insulating film is formed by a silicon nitride film formed by a low-pressure CVD method. By the provision of such a first insulating film, it is possible to suppress or prevent water or hydrogen ions from diffusing to the floating gate electrode, and therefore, the data retention characteristics of a flash memory can be improved.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: June 8, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Shiba, Hideyuki Yashima
  • Patent number: 7731005
    Abstract: The present invention provides a lock-up clutch mechanism for a torque converter, in which a plurality of friction materials are arranged concentrically in a radial direction and adjacent friction materials are integrally connected to each other.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: June 8, 2010
    Assignee: NSK-Warner K.K.
    Inventor: Ritsuo Toya
  • Patent number: 7733473
    Abstract: An inspection apparatus includes a wafer stage for carrying a wafer, an illumination module which irradiates an inspection beam on the wafer carried on the wafer stage, a detection module which detects scattering rays or reflection rays from the wafer on the wafer stage and outputs an image signal, a coordinates control module which stores information about the arrangement of individual inspection areas on the wafer, and an imperfect area recognition module which recognizes, on the basis of the inspection area arrangement information stored in the coordinates control module, an imperfect inspection area interfering with a wafer edge.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: June 8, 2010
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hiroyuki Yamashita, Yukihisa Mohara, Eiji Imai