Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7701376
    Abstract: In a wireless chip receiving the multi-rate data according to the related art, power consumption and a circuit area of an analog-to-digital converter become large. In a digital calibration type analog-to-digital converter including both a reference analog-to-digital conversion unit and a main analog-to-digital conversion unit, when processing the high-sample rate wireless receive signal, both the reference analog-to-digital conversion unit and the main analog-to-digital conversion unit are operated to configure a general digital calibration type analog-to-digital converter, and when processing a low-sample rate wireless receive signal, analog-to-digital conversion is performed by using the reference analog-to-digital conversion unit and operations of the main analog-to-digital conversion unit or the like are stopped to remarkably reduce power consumption.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: April 20, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Oshima, Taizo Yamawaki
  • Patent number: 7699180
    Abstract: A layout for packaging a computer rack comprises a transport pallet (2) and a computer rack; the computer rack being associable with casters extending vertically by a first distance relatively to a lower face of the rack. The computer rack is made integral with the pallet by two anchoring means distributed on the underside of the rack on either side of a vertical median plane (P1); the pallet includes two side modules and an intermediate supporting means separable from the remainder of the pallet and allowing the side modules to be connected. The side modules are removably attached to the anchoring means, so as to ensure that the computer rack is maintained in a horizontal position, and that the pallet is spaced away from the underside of the rack by a second distance (H2) smaller than said first distance.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: April 20, 2010
    Assignee: Bull S.A.S.
    Inventors: Emmanuel Mollard, Lionel Coutancier
  • Patent number: 7702704
    Abstract: A random number generating method for an electronic device including a plurality of unit circuits each first and second logic circuits, each logic circuit having a same shape and being formed through a same fabrication process, and an amplifier circuit for forming a binary signal by amplifying a noise superposed on the differential voltage of threshold voltages of the first and the second logic circuits; and a signal variation detecting circuit for forming an output signal in response to a variation in any of a plurality of binary signals outputted from the plurality of unit circuits, wherein a plurality of binary signals outputted from the signal variation detecting circuit are combined to generate a random number.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: April 20, 2010
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventor: Masaya Muranaka
  • Patent number: 7691677
    Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Patent number: 7691272
    Abstract: A method of effecting efficient flow equalization in a settling and retention basin having a peripheral wall housing a removable design flow equalization port and a filter member exteriorly of the peripheral wall by (a) observing the height of liquid level induced during wastewater flow upon the filter member relative to the flow equalization port. Thereafter (b) determining whether the observed height of step (a) is outside a desired optimum height range reflective of meeting the design flow characteristics of the design flow port. Thereafter (c) replacing the design flow equalization port with a different size flow equalization port based upon the performance of step (b).
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: April 6, 2010
    Inventor: Jan D. Graves
  • Patent number: 7691211
    Abstract: The present invention concerns a method for generating nanostructures in order to obtain in an area on the surface of a metal piece (10) a nanostructured layer of defined thickness, characterized in that it comprises: a step for projecting onto an impact point in the area of the surface of the piece (10) to be treated, for a given duration, at a given speed and at variable incidences at the same impact point, a given quantity of perfectly spherical balls (22) of given dimensions, reused continuously during the projection; repetition of the preceding step with a shift of the impact point so that the impact points as a group cover the entire surface of the piece to be treated; a step for treatment by diffusion of chemical compounds into the nanostructured layer generated during the step for implementing the method for generating nanostructures.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: April 6, 2010
    Assignees: Universite de Technologie de Troyes, The Institute of Metal Research
    Inventors: Jian Lu, Ke Lu
  • Patent number: 7691864
    Abstract: Pharmaceutical compositions for the treatment of hypertension comprising an effective anti-hypertensive amount of at least one compound in association with a pharmaceutically acceptable, substantially non-toxic carrier or excipient, the compound having one of the formulae (I), (II), (III) or (IV), and methods for the treatment of hypertension or effecting anti-hypertensive action which comprises administering to a patient requiring anti-hypertensive therapy or effect at least one of the above-described compounds.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: April 6, 2010
    Assignee: University of Florida
    Inventor: Raymond J. Bergeron, Jr.
  • Patent number: 7692233
    Abstract: A technology capable of improving a charge retention characteristic of a nonvolatile memory is provided. In a memory cell in which an interlayer insulating film formed of an ONO film obtained by laminating a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film is formed between a floating gate formed of a polycrystalline silicon film and a control gate formed of a polycrystalline silicon film, the upper silicon oxide film is formed through LPCVD and is then nitrided through a remote plasma process, thereby introducing nitrogen of, for example, 5 to 6 atom % into the upper surface portion of the upper silicon oxide film.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kobayashi, Toshiyuki Mine
  • Patent number: 7692456
    Abstract: A semiconductor integrated circuit having a plurality of ultrasound pulsers corresponding to a plurality of respective channels, and integrally formed on a small area. The ultrasound pulsers each include a MOSFET gate drive circuit in which an input voltage pulse is converted into a current pulse, and the current pulse is converted again into a voltage pulse on the basis of a high potential side voltage +HV, and a low potential side voltage ?HV, applied to a transducer drive circuit, and in which a voltage level shift in the input voltage pulse is attained, and a voltage pulse swing is generated by the MOSFET gate drive circuit on the basis of the high potential side voltage +HV, and the low potential side voltage ?HV. The MOSFET gate drive circuit is DC-coupled with the transducer drive circuit.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: April 6, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Hanazawa, Hiroyasu Yoshizawa
  • Patent number: 7693004
    Abstract: This invention discloses a semiconductor memory device having a voltage supply circuit for generating a driver power supply voltage. The voltage supply circuit is provided with a first voltage supply circuit for precharging the driver power supply voltage to a power supply voltage level of a memory cell, and a second voltage supply circuit for supplying a voltage lower than the power supply voltage level of the memory cell as the driver power supply voltage.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: April 6, 2010
    Assignee: Renesas Technology Corp.
    Inventor: Masaki Tsukude
  • Patent number: 7694194
    Abstract: A highly reliable semiconductor device includes, for example, a memory circuit MEM such as a multiport RAM and a BIST circuit (BIST[A] and BIST[B]) for carrying out a test for each of the ports PO[A] and PO[B] of the MEM, as well as pointers PNT0[A] to PNT3[A] and PNT0[B] to PNT3[B] corresponding to the PO[A] and PO[B], respectively. Each of the BIST[A] and BIST[B] manages plural respective segments SEG0 to SEG3 obtained by dividing the MEM and the PNT0[A] to PNT3[A] are provided for those SEG0 to SEG3, respectively. For example, the BIST[A], upon accessing SEG0, writes ‘1’ in PNT0[A] while the BIST[B] refers to the value in this PNT0[A], thereby its access to SEG0 can be avoided. Consequently, each port can execute a complicated test pattern asynchronously.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: April 6, 2010
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventors: Hideki Hayashi, Mitsuo Serizawa
  • Patent number: 7693000
    Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: April 6, 2010
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd
    Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
  • Patent number: 7686778
    Abstract: One or more waste balancing systems may be used in a fluid circulating system for medical use. The fluid circulating system may be part of a blood treatment system for a patient suffering renal failure. A waste balancing system may include a pressure element operable to maintain a constant fluid pressure created by the combined weight of waste removed from a patient and replacement fluid for providing to a patient. Multiple evaluation characteristics or control parameters may be evaluated or controlled for safety and accuracy. At least part of the waste balancing system may be incorporated into a disposable cartridge.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: March 30, 2010
    Assignee: NxStage Medical, Inc.
    Inventors: Jeffrey H. Burbank, James M. Brugger
  • Patent number: 7686393
    Abstract: An orthopedic back support for displacing a person's weight from the lower area of the spine by providing support for the upper torso and for use with a chair or seat having a seat base and a seat back. A flexible fabric cross piece is connected between vertical members to provide back. The cross piece may include vertical channels or sleeves at opposite sides to receive and support the vertical members. A flexible strap is connected to the fabric or the vertical members and adapted to be positioned behind a seat or a head rest. The entire unit is portable or may be fabricated as part of a seat.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 30, 2010
    Inventor: John G. Rutty
  • Patent number: 7688086
    Abstract: To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: March 30, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Motoyama, Yoshimi Horigome, Seigo Nakamura, Iwao Natori
  • Patent number: 7687850
    Abstract: This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to the upper oxide film. A second cavity is disposed, in a position between the nitride film and a substrate and below an end portion of the memory gate, adjacent to the bottom oxide film. These cavities are closed with sidewall spacers formed over the substrate along the sidewalls of the memory gate.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: March 30, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasushi Ishii, Takashi Hashimoto, Koichi Toba, Yoshiyuki Kawashima
  • Patent number: 7686360
    Abstract: An apparatus for waste collection and disposal including a tube portion which includes a longitudinal axis, a first end defining a first opening, a second end defining a second opening, an outer side, and an inner side defining a channel between the first and second ends. The apparatus for waste collection and disposal also including a scoop portion coupled to the first end of the tube portion, a plurality of clips coupled to the outer side of the tube portion, and a handle portion coupled to the outer side of the tube portion.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: March 30, 2010
    Inventor: Sheri L. Platt
  • Patent number: 7685407
    Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Goro Sakamaki, Yuri Azuma
  • Patent number: 7681484
    Abstract: In accordance with an embodiment of the present invention, a blast-resistant panel may include a layer of a pre-cured elastomeric material having a predetermined thickness, a body portion, and a plurality of flanges, each of the plurality of flanges having a substantially equal width and depending away from a same side and at approximately equivalent right angles to the body portion. The blast-resistant panel may also include a plurality of fastener elements for securing the pre-cured elastomeric material layer to a surface of a structure through the plurality of flanges of pre-cured elastomeric material layer.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: March 23, 2010
    Assignee: Life Shield Engineered Systems, LLC
    Inventor: Bruce Hall
  • Patent number: 7683723
    Abstract: A PLL circuit equipped with a loop gain detecting circuit that can suppress the change of the loop gain. When detecting the loop gain, the frequency of the input signal to the second input (IN-2) of the phase detector is first changed, and the response corresponding to the change is detected by the output of the voltage locked oscillator. The detection is performed by connecting the output of the voltage locked oscillator with the counter and connecting the output of the counter with the integrator. The phase locked loop characteristics are optimized by performing feedback for the detection result on the value of the charge pump current.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: March 23, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yukinori Akamine, Manabu Kawabe, Satoshi Tanaka, Yasuo Shima, Ryoichi Takano