Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

Abstract: A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance.

Abstract: There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Abstract: A charge holding insulating film in a memory cell is constituted by a laminated film composed of a bottom insulating film, a charge storage film, and a top insulating film on a semiconductor substrate. Further, by performing a plasma nitriding treatment to the bottom insulating film, a nitride region whose nitrogen concentration has a peak value and is 1 atom % or more is formed on the upper surface side in the bottom insulating film. The thickness of the nitride region is set to 0.5 nm or more and 1.5 nm or less, and the peak value of nitrogen concentration is set to 5 atom % or more and 40 atom % or less, and a position of the peak value of nitrogen concentration is set within 2 nm from the upper surface of the bottom insulating film, thereby suppressing an interaction between the bottom insulating film and the charge storage film.

Abstract: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method.

Abstract: The present invention relates to novel crystalline modifications of N-?-(2,4,6-triisopropylphenylsulfonyl)-3-hydroxyamidino-(L)-phenylalanine 4-ethoxycarbonylpiperazide and/or salts thereof, which can be used as pharmaceutical agents, and to pharmaceutical compositions and pharmaceutical uses comprising these novel crystalline modifications.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.

Abstract: Disclosed herein is a semiconductor integrated circuit device such as a for-camera preprocessing LSI suitable for a semiconductor integrated circuit and having improved responsiveness. In a D/A converter circuit for generating a feedback signal for compensating for black level variation in a for-camera preprocessing LSI, first-conductivity-type MOSFETs as first current sources produce currents corresponding to digital signals. The digital signals are supplied to first-conductivity-type first differential MOSFETs and second-conductivity-type second differential MOSFETs, with the gates and drains of the first differential MOSFETs and the gates and drains of the second differential MOSFETs being connected together respectively.

Abstract: It is an object to realize smooth switching between free scanning and high speed scanning in a light scanning apparatus and a light scanning microscope. To attain the object, a light scanning apparatus includes at least three mirror scanners disposed at predetermined positions of a light path for light scanning, and a light path switching unit switching the light path between a light path in which a highest-speed mirror scanner among the mirror scanners is valid and a light path in which the highest-speed mirror scanner is invalid. Therefore, the switching between a free scanning mode and a high speed scanning mode is performed by the driving of the light switching unit and involves no movement of galvanometer scanners. In addition, since the resonant galvanometer scanner is invalid during the free scanning mode, it is possible to make the resonant galvanometer scanner on standby.

Abstract: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d?0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.

Abstract: A semiconductor device which includes: a semiconductor chip with plural pads; a tab connected with the semiconductor chip; bus bars which are located outside of the semiconductor chip and connected with the tab; a sealing body which resin-seals the semiconductor chip; plural leads arranged in a line around the semiconductor chip; plural first wires which connect pads of the semiconductor chip and the leads; and plural second wires which connect specific pads of the semiconductor chip and the bus bars. Since the sealing body has a continuous portion which continues from a side surface of the semiconductor chip to its back surface to a side surface of the tab, the degree of adhesion among the semiconductor chip, the tab and the sealing body is increased. This prevents peeling between the tab and the sealing body during a high-temperature process and thus improves the quality of the semiconductor device (QFN).

Abstract: Providing an optical system having a large aperture ratio, a long back focal length, high optical performance with excellently correcting various aberrations, and an optical apparatus equipped with the optical system. The system includes, in order from an object along an optical axis of the optical system, a first lens group having positive refractive power, and a second lens group having positive refractive power. The second lens group includes a negative lens, a first positive lens, and a second positive lens, and the optical system includes a compound type aspherical lens constructed by a glass material and a resin material.

Abstract: If memory cell blocks are laid out in a conventional manner to create a memory chip with a capacity of an odd power of 2 by using memory cells whose aspect ratio is 1:2, the chip will take a 1:1 shape and become difficult to enclose in a package of a 1:2 shape. In addition, such conventional layout of memory cell blocks to form the 1:2 shape causes the area of a peripheral circuit region to be limited by the memory blocks, pads to be arranged collectively in the central section of the chip, and wiring to become dense during the enclosure of the chip in the package. In this invention, therefore, four memory blocks, BANK0, BANK1, BANK2, BANK3, BANK3, are constructed into an L shape and then these memory blocks are properly combined and arranged to construct a chip of nearly a 1:2 shape in terms of aspect ratio.

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate.

Abstract: For an internal circuit having a first operation mode consuming a first operational current and a second operation mode consuming a second operational current, which is smaller than the first operational current, a first power source regulator for stepping down a predefined output power supply voltage from an input power supply voltage and having a current supply ability corresponding to the first operational current of the internal circuit and a second power source gulator having a current supply ability corresponding to the second operational current are combined in order to, under the control of a power supply control unit, operate the first step-down type regulator in response to a first control signal instructing the first operation mode in the internal circuit and to operate the second step-down type regulator in response to a second control signal instructing the second operation mode.