Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

Abstract: A settling and retention basin includes an interior chamber having a peripheral wall preferably provided with two diametrically opposite openings in each of which is received a flow port member having a flow equalization port therein. Depending upon wastewater levels and surges, the flow port members can be removed and replaced by other flow port members of an identical construction, except for different sizes of design flow equalization ports thereof.

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract: A self-cleaning assembly comprising an enclosed casing 1 with a movable piston 31 and filters 32,33 therein. The preferred assembly has a casing 1 with a dirty water inlet 5, a first outlet 6 for clean filtered water and a second outlet 7 for the removal of sludge from the casing. The filter assembly is constructed and arranged to provide, in its normal operating mode, a liquid flow path through the filter 32,33 in a first direction between the dirty water inlet 5 and the clean water outlet 6 and, in a cleaning mode, to provide a liquid flow path in a second direction between the dirty water inlet 5 and the sludge outlet 7. In the cleaning mode, the movable member 31 compresses the filters 32,33 during the liquid flow in the second direction and contaminant is released therefrom for removal from the filter assembly via the second outlet 7. In an alternative embodiment, the sludge outlet 7 is omitted and sludge is removed from the casing via the outlet 6.

Abstract: An object is to provide a technology capable of improving a manufacturing yield of semiconductor devices by preventing scattering of irregular-shaped scraps formed at the time of dicing. To achieve the above object, for dicing lines, by which an irregular-shaped outer periphery may possibly be cut off, among a plurality of dicing lines, formation of the dicing lines starts from an outside of a semiconductor wafer, and after the semiconductor wafer is cut off partway, formation of the dicing lines is ended before reaching the irregular-shaped outer periphery formed on a outer periphery of the semiconductor wafer. For other dicing lines, formation of the dicing lines starts from the outside of the semiconductor wafer, and after the semiconductor wafer is cut off, is ended outside the semiconductor wafer.

Abstract: Providing a large aperture wide-angle lens having high optical performance with sufficiently suppressed spherical aberration and sagittal coma flare, and an imaging apparatus using the lens. The lens including, in order from an object, a first lens group having positive refractive power, and a second lens group having positive refractive power, the second lens group being movable for focusing and including a 21 lens component having positive refractive power, a 22 lens component having negative refractive power, a 23 lens component having positive refractive power, and a 24 lens component having positive refractive power, and given conditions being satisfied.

Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.

Abstract: A compact zoom lens system has a zoom ratio of about 3.5 or more, an angle of view of 29° or more in a wide-angle end, and a vibration reduction function. The system includes, in order from an object, a first group having positive power, a second group having negative power, and a third group having positive power. Upon zooming from a wide-angle end to a telephoto end, a distance between the first and second groups increases, and a distance between the second and third groups decreases. The third group consists of, in order from the object, a 31 group having positive power, a 32 group having negative power, and a 33 group. Only the 32 group is moved perpendicularly to an optical axis for correcting image blur due to camera shake.

Abstract: In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.

Abstract: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

Abstract: The present invention provides a voltage clamping circuit which is operated in a stable manner with the simple constitution and a switching power source device which enables a high-speed operation. In a switching power source device, one of source/drain routes is connected to an input terminal to which an input voltage is supplied, a predetermined voltage to be restricted is supplied to a gate, and using a MOSFET which provides a current source between another source/drain route and a ground potential of the circuit, a clamp output voltage which corresponds to the input voltage is obtained from another source/drain route. The switching power source device further includes a first switching element which controls a current which is made to flow in an inductor such that the output voltage assumes a predetermined voltage and a second switching element which clamps an reverse electromotive voltage generated in the inductor when the first switching element is turned off to a predetermined potential.

Abstract: A pulse generator for UWB transmission, lower power consumption, and suppression of LO leakage by nonuse of the LO signal. The pulse generator includes a clock generator (CLK) for giving clock of a predetermined period; a delay circuit (DLY) equipped with a function of controlling a delay time and for delaying the clock; a square-wave pulse generation circuit (SWPG) that receives information being spread by a spread code and modulates phases of square wave pulses that have a pulse width corresponding to a differential delay for one stage of the delay circuit; and an amplitude control unit (AMPC) that outputs an impulse sequence having the pulse width of the square wave in a predetermined amplitude and combines the impulses; and outputs pulses that have a predetermined envelope form.

Abstract: An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable.

Abstract: A weight of an inertial sensor if formed from a plurality of divided weights, and the divided weights are connected to each other by elastically deformable beams. A movable range and a mass of each of the divided weights and a rigidity of each of the beams are adjusted and a plurality of deformation modes having different sensitivity ranges with respect to the acceleration are used in combination. By this means, it is possible to improve a detecting sensitivity of an acceleration and widen an acceleration response range.

Abstract: A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

Abstract: A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side opposite to the one side of the semiconductor chip. The reduction in size of the semiconductor device can be attained.

Abstract: This invention provides a semiconductor memory device with enhanced speed performance or enabling timing adjustment reflected in characteristic variation of memory cells, adapted to suppress an increase in the number of circuit elements. A write dummy bit section comprises a first dummy line and a second dummy line corresponding to complementary bit lines and a plurality of first dummy cells formed to be similar in shape to static memory cells, wherein a write current path is coupled between the first dummy line and the second dummy line. In the write dummy bit section, one voltage level is input to the first dummy line through driver MOSFETs in relation to write signal inputs to the static memory cells and a signal change in the second dummy line precharged at the other voltage level is sensed and output. A timing control circuit deselects a word line selected by an output signal from the write dummy bit section.

Abstract: Providing a retrofocus lens system and an image-taking device having small variation in aberrations upon focusing on a close object with a high imaging magnification. The retrofocus lens system includes, in order from an object, a first lens group G1 having negative refractive power, a second lens group G2 having negative refractive power, and a third lens group G3 having positive refractive power. Upon focusing from infinity to a close object, the first lens group G1, the second lens group G2, and the third lens group G3 are moved to the object such that a distance between the first lens group G1 and the second lens group G2 increases, and a distance between the second lens group G2 and the third lens group G3 decreases.

Abstract: A process yield of a semiconductor device is enhanced. To that end, there is provided a semiconductor device comprising a substrate having a component mount face with semiconductor chips mounted thereon, the substrate being provided with a plurality of connection leads, and a cap made of resin, placed over the component mount face of the substrate so as to cover the same, the a cap having a first body part, and a second body part larger in thickness than the first body part. Because product information in the form of inscriptions is engraved on the top surface side of the second body part of the cap, the product information can be displayed without the use of an ink mark, it is possible to prevent occurrence of marking defects due to ink bleed, and so forth, thereby enhancing the process yield of a memory card (the semiconductor device).