Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7652360
    Abstract: An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: January 26, 2010
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 7653709
    Abstract: The invention relates to a method for processing a complex request addressed to at least one SNMP agent (5) of a resource machine (2b) from an SNMP manager (4) of an application machine (2a). The complex request is processed so as to enable an integrating agent (6) to translate the complex request into SNMP requests and to optimize the number of SNMP requests transmitted through the network (3), particularly the number of GETNEXT requests.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: January 26, 2010
    Assignee: Thomson Licensing S.A.
    Inventor: Olivier Miakinen
  • Patent number: 7652917
    Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasushi Oka, Kazuyoshi Shiba
  • Patent number: 7652863
    Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
  • Patent number: 7650977
    Abstract: The present invention provides a friction plate for a wet-type multi-plate clutch, to which a wet-type friction material is secured and in which there are provided an oil passage communicated with inner and outer peripheral edges, an oil groove opened toward the inner peripheral edge and having a terminal end disposed between the inner peripheral edge and the outer peripheral edge, and at least one circumferential groove communicated with the oil passage and extending in a circumferential direction.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: January 26, 2010
    Assignee: NSK-Warner K.K.
    Inventors: Hideaki Suzuki, Masahiro Kobayashi, Masaki Sakabe
  • Patent number: 7652924
    Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yoshiki Kawajiri, Masaaki Terasawa, Takanori Yamazoe
  • Patent number: 7650845
    Abstract: A device for protecting a boat hull has an inflatable element with a deflated state, in which the element can be positioned either inside or outside of the boat hull. When located outside the hull, the inflatable element is operatively connected to an inflation/deflation circuit by a conduit. A translational control device causes the inflatable element to be selectively positioned between a position inside the hull and a position outside the hull. When outside the hull, the inflatable element may be inflated or deflated by the inflation/deflation circuit. A bushing provides a through opening in the hull through which the conduit and deflated element pass. A weighted plug is provided at the end of conduit and is shaped to provide sealing engagement with the bushing.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: January 26, 2010
    Inventors: Jean Luc Vanoise, Alain Delepouve
  • Patent number: 7652333
    Abstract: The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit (6) and a power-supply-uninterrupted circuit (7). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch (10) between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Osamu Ozawa, Toshio Sasaki, Ryo Mori, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi
  • Patent number: 7648384
    Abstract: An electrical hook-up device including an outlet, a plug and a tight-seal casing with a cover and a shutter and enabling a tightly sealed hook-up of the plug in the outlet. The casing takes the form of an accessory removably mounted on the outlet, and the shutter of said casing is also movably mounted on the cover.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: January 19, 2010
    Assignees: Legrand France, Legrand SNC
    Inventors: Olivier Desissard, Sébastien Dupuy
  • Patent number: 7648432
    Abstract: This patent application is for a baseball and softball home plate system generally, and more specifically a home plate system with changeable top plate sections and an up-tight bevel.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: January 19, 2010
    Inventor: Roger E. Hall
  • Patent number: 7646662
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: January 12, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 7646197
    Abstract: To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: January 12, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Misaka, Makoto Saen, Tetsuya Yamada, Keisuke Toyama, Kenichi Osada
  • Patent number: 7646085
    Abstract: A semiconductor device includes external interface terminals and processing circuits, and it is fed with an operating power source when detachably set in a host equipment. Power source feeding terminals (VCC, VSS) among the external interface terminals are long enough to keep touching the corresponding terminals of the host equipment for, at least, a predetermined time period since the separation of an extraction detecting terminal among the external interface terminals, from the corresponding terminal of the host equipment, and they are formed to be longer in the extraction direction of the semiconductor device than the extraction detecting terminal. Thus, a time period till the cutoff of the power source is easily made comparatively long. The power source feeding terminals should preferably be extended onto the insertion side of the semiconductor device, but an extendible distance is sometimes liable to be limited.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 12, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Kenji Osawa, Hideo Koike, Junichiro Osako, Tamaki Wada
  • Patent number: 7644351
    Abstract: Systems and methods for data collection and processing. A system includes a forms processing subsystem including a form designer and a form processing and workflow module, and a client subsystem including a form submission manager and a client data store. User provided information is maintained locally in the client data store.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: January 5, 2010
    Assignee: Information Sciences Corporation
    Inventors: Gregory Portnoy, Richard A. Wiseman
  • Patent number: 7641033
    Abstract: The present invention provides a wet type multi-plate clutch comprising a first friction engaging element coaxially arranged within a clutch housing, a second friction engaging element alternately disposed with the first friction engaging element and a piston for applying an axial load to engage the first and second friction engaging elements with each other and wherein a projection protruding toward the piston is provided on the clutch housing and a recessed portion is provided in the piston so that a relative rotation between the clutch housing and the piston is prevented by engaging the projection with the recessed portion.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: January 5, 2010
    Assignee: NSK-Warner K.K.
    Inventor: Kiyokazu Ichikawa
  • Patent number: 7639525
    Abstract: A semiconductor memory device for reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode is provided. The semiconductor memory device also prevents an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area, and ensures stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: December 29, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Patent number: 7638137
    Abstract: A drug delivery system comprising a contact lens having dispersed therein as nanoparticles having a particle size less than about 50 nm, an ophthalmic drug nanoencapsulated in a material from which said ophthalmic drug is capable of diffusion into and migration through said contact lens and into the post-lens tear film when said contact lens is placed on the eye.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: December 29, 2009
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Anuj Chauhan, Derya Gulsen
  • Patent number: 7634874
    Abstract: A collapsible structural member has been provided in which substantially identical modules made up of metal or plastic are threaded on a tensioning member such as a cable and are movable relative to each other in the collapsed condition of the beam and are brought together into a condition where adjacent modules are locked together to form a rigid construction when the beam is in its erected operating condition. The beam is changed from its erected condition to its collapsed condition by relaxing the tensioning member or cable.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: December 22, 2009
    Assignee: Luco-Ed Enterprises LLC
    Inventor: Nicholas G. Lucas
  • Patent number: 7633315
    Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: December 15, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Patent number: 7632744
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Grant
    Filed: April 14, 2008
    Date of Patent: December 15, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida