Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7443218
    Abstract: A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit, which is a comparator circuit, during a period when the pulsed clock is at a high level, and the dynamic XOR circuit is cut off during a period when the pulsed clock is at a low level.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masafumi Onouchi, Yusuke Kanno, Hiroyuki Mizuno, Yasuhisa Shimazaki, Tetsuya Yamada
  • Patent number: 7443721
    Abstract: A semiconductor non volatile memory device capable of multiple write operations with high reliability includes memory cells. Each memory cell of the device has a first electrode, a second electrode, and an information storage section between the two electrodes. A segregation of composing elements of the information storage section caused by applying a first current pulse from the first electrode to the second electrode is corrected by applying a second current pulse from the second electrode to the first electrode such that the composition of the storage section recovers to its original state.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kenzo Kurotsuchi, Kiyoo Itoh, Norikatsu Takaura, Kenichi Osada
  • Patent number: 7442989
    Abstract: This invention is intended to improve reliability of a nonvolatile semiconductor memory device and reduces a memory cell size of the nonvolatile semiconductor memory device. A memory cell which includes source/drain diffusion layers in a p-type well formed in a silicon substrate, silicon nitride dots which are located between silicon oxide films and into which charges are injected, a control gate 212, and assist gates is formed. Programming is conducted to the memory cell by injecting electrons into the drain-side silicon nitride dots or the source-side silicon nitride dots. Since silicon nitride serving as a charge injected section is in the form of dots, it is possible to suppress movement of the charges in a channel direction, to prevent the charges on a source end portion and those on a drain end portion from being mixed together, and to improve charge holding characteristic of the memory cell. Even in the case where a gate length is shortened, the charge holding characteristic can be secured.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kobayashi, Toshiyuki Mine
  • Patent number: 7443731
    Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
  • Patent number: 7442986
    Abstract: In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kan Yasui, Digh Hisamoto, Shinichiro Kimura
  • Patent number: 7443159
    Abstract: An inductive sensor for detecting the position of a vehicle seat or for a gate shifting unit of an automatic transmission is described. The inductive sensor unit has a plurality of sensor coils that are disposed in planar fashion on a printed circuit board A conductive actuation element is guided, spaced apart, in a path over the sensor coils and an electrical evaluation circuit detects changes in inductance of the sensor coils in accordance with the path position of the actuation element and converts the changes into electrical signals corresponding to seat position signals on gear shifting signals. The actuation element is guided along the sensor coils with conductive bottom faces that are staggered in the direction of the path.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: October 28, 2008
    Assignee: Cherry GmbH
    Inventors: Josef Habenschaden, Hans-Ludwig Götz, Thomas Luber
  • Patent number: 7444123
    Abstract: With a dual mode transmitter capable of handling two modulation methods for nonconstant amplitude modulation and constant amplitude modulation, respectively, speed-up of transition between modes is implemented. In a mode handling the constant amplitude modulation, first capacitors included in a low-pass filter constituting an AM loop, and a second capacitor included in an integrator are kept recharged from a first constant-voltage power supply and a second constant-voltage power supply by use of a first switch and a second switch, respectively. By doing so, a value of voltage to be recharged at the time of a mode changeover is decreased, and further, a first variable-gain amplifier starts control of a gain while avoiding a region where the output voltage of the first variable-gain amplifier has slow response against an input voltage.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Taizo Yamawaki, Yoshiaki Harasawa
  • Patent number: 7440350
    Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: October 21, 2008
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tadahiro Obara, Masatoshi Hasegawa, Yousuke Tanaka, Tomofumi Hokari, Kenichi Tajima
  • Patent number: 7439622
    Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 21, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hitoshi Akamine, Masashi Suzuki, Masao Yamane, Tetsuaki Adachi
  • Patent number: 7441184
    Abstract: A method for internationalizing a markup document includes detecting a localization tag in the document, retrieving localization information from the document which is associated with the localization tag, searching a translation file for a localized value associated with the localization information, and replacing the localization tag in the document with the localized value found in the translation file. The localization information includes any one or more of a localization attribute, a default localization value, and a value corresponding to an automatic transcription function. A system for internationalizing the markup document includes a first storage unit which stores the markup document, a second storage unit which stores the translation file, and a localization tool which localizes the markup document stored in the first storage unit based on information in the translation file stored in the second storage unit.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: October 21, 2008
    Assignee: Bull S.A.
    Inventors: Laurent Frerebeau, Luc Creti
  • Patent number: 7437569
    Abstract: A module for secure management of digital data by encryption/decryption and/or signature/verification of signature which can be used for dedicated servers. The module is controlled by a microprocessor (?P1). A working memory (RAM) is associated with the microprocessor and is provided with a common interfacing module. Parallel-connected to this common interfacing module and forming the internal circuits of said module are a plurality of circuits for secure management of data received from or respectively transmitted to the common interfacing module. Each secure management circuit forming an automatic secure management device is equipped with a secure management input/output sub-module connected to the common interfacing module and a specific sub-module for encryption/decryption or respectively for calculation/verification of signature.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: October 14, 2008
    Assignee: Bull, S.A.
    Inventor: Patrick Le Quere
  • Patent number: 7437602
    Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: October 14, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shinsuke Asari, Chiaki Shinagawa, Yasuhiro Nakamura, Motoki Kanamori, Atsushi Shiraishi
  • Patent number: 7436716
    Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: October 14, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Koji Kishi, Hideaki Kurata, Satoshi Noda, Yusuke Jono
  • Patent number: 7436722
    Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: October 14, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
  • Patent number: 7430600
    Abstract: The present invention presents a device and a method for handling security in a computer system comprising an existing organizational directory. Upon reception of an access request from an entity to a server machine of the system, the device creates or searches in a security directory for security data attached to the entity, without modifying the data of the existing directory.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: September 30, 2008
    Assignee: BULL, S.A.S.
    Inventors: Hatem Trabelsi, Philippe Dutrueux
  • Patent number: 7429060
    Abstract: A telescopic shaft for steering of a vehicle is assembled in a steering shaft and includes a male shaft and a female shaft that are so fitted as not to be rotatable but to be slidable. Rolling members are fitted through an elastic body for pre-load between at least a pair of axially-extending grooves formed in an outer peripheral surface of the male shaft and in an inner peripheral surface of the female shaft. A slide member is fitted in between at least another pair of axially-extending grooves formed in the outer peripheral surface of the male shaft and in the inner peripheral surface of the female shaft. When a steering toque is equal to or smaller than a predetermined level, the elastic body for the pre-load exhibits a low rigidity characteristic as the elastic body performs pre-load action. When the steering torque is equal to or larger than the predetermined level, the slide member exhibits a high rigidity characteristic as the slide member engages with the pair of axially extending grooves.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: September 30, 2008
    Assignee: NSK Ltd.
    Inventors: Yasuhisa Yamada, Akihiro Shoda, Atsushi Ozawa, Takatsugu Yamada
  • Patent number: 7427032
    Abstract: An adapter for a memory card is disclosed which performs a change of size so that a memory card smaller in planar size but almost equal in thickness as compared with a multi-media card can be used as a multi-media card. A protuberant portion is formed behind plural external terminals formed on a back side of the adapter, whereby, while the thickness of a front side of the adapter is maintained at a standardized thickness of the multi-media card, a rear side of the adapter is made thicker than the front side and internal terminals for contact with external terminals of the memory card are disposed in the interior of the thick portion of the adapter. The versatility of an extremely small-sized memory card can be improved.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: September 23, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Junichiro Osako, Hirotaka Nishizawa, Kenji Osawa, Hideo Koike
  • Patent number: 7426986
    Abstract: A one-way clutch of package type which includes a one-way clutch comprising an inner race, an outer race and a torque transferring member for transferring torque between the inner race and the outer race and in which a bearing is integrally incorporated between the inner and outer races of the one-way clutch and wherein a biasing member is interposed between an axial end face of at least one of projections of the inner and outer races of the one-way clutch and an axial end face of an inner race or an outer race of the bearing.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: September 23, 2008
    Assignee: NSK-Warner K.K.
    Inventor: Toshio Awaji
  • Patent number: 7426343
    Abstract: The present invention relates to a holographic optical element (8), a viewfinder display (5, 6, 7) of a camera (1) using thereof, and a camera (1). The purpose of the present invention is to show various superimposed displays for various information with securing a bright viewfinder image. In the holographic optical element according to the present invention, a liquid crystal (13) whose orientation is changeable and a liquid crystal (14) whose orientation is fixed are arranged alternately with a striped shape between the transparent members (12a) (12b) on which the transparent electrodes (11a) (11b) are formed facing with each other.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: September 16, 2008
    Assignee: Nikon Corporation
    Inventor: Itaru Homma
  • Patent number: D577908
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: October 7, 2008
    Assignee: Gamewear, Inc.
    Inventors: Frank Cerullo, Nick Iovacchini