Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7482850
    Abstract: A technology capable of avoiding malfunction of a delay locked loop without generating a constant phase error in a delay locked loop circuit is provided. In a delay locked loop circuit, a control circuit is disposed in the outside of a delay locked loop, and in phase comparison of the delay locked loop, the control circuit outputs a control signal to the delay locked loop so that the relation in the phase comparison between a reference signal and an output signal is shifted by a set cycle.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: January 27, 2009
    Assignee: Renesas Technology Corp.
    Inventor: Takashi Kawamoto
  • Patent number: 7483297
    Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.
    Type: Grant
    Filed: October 13, 2007
    Date of Patent: January 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Mori, Seisuke Hirosawa, Atsushi Shikata
  • Patent number: 7478473
    Abstract: The productivity of an IC card is to be improved. In a memory card of the type in which a memory body having a wiring substrate and a semiconductor chip mounted on a main surface of the wiring substrate is held so as to be sandwiched in between a first case and a second case, a planar outline of the memory body is smaller than half of a planar outline of the memory card. The memory body is disposed so as to be positioned closer to a first end side as one short side of the memory card with respect to a midline between the first end side and a second end side as an opposite short side of the memory card positioned on the side opposite to the first end side. The other area than the memory body-disposed area in the first and the second case is used as another functional area.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: January 20, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Kenji Osawa, Akira Higuchi, Junichiro Osako, Tamaki Wada
  • Patent number: 7477732
    Abstract: The invention concerns a method which consists in introducing for each registered user a profile comprising filtering and agenda data, determining and updating an accessibility status of each registered user terminal (10, 11), depending on whether the latter is accessible or not through a network, and following a call by a caller to the registered user: determining an availability status of the called user depending on whether the caller is authorized to communicate with the called party on the basis of the called party's profile data, and an identification of the caller, if the called party is not accessible or does not authorize the caller to complete his call, proposing to the caller to be automatically put through to the called party, when the latter will be accessible and available for the caller, if the latter agrees, triggering an automatic recall procedure enabling to put through the caller's call (17) to the called party.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 13, 2009
    Assignee: France Telecom
    Inventors: Emmanuel Bury, Alan Kerdraon, Jacques-Olivier Rebillon, Eric Flammant
  • Patent number: 7477525
    Abstract: A system for maintaining an assembly of three aligned parts (1, 2, 3) in position, wherein a latching device (4) receives a joining member (6) integral with a rear part (1) of the assembly. The latching device (4) can slide on the joining member and is mounted inside a front part (3) and joined by springs (5) to the front part. The system includes means for moving the locking device, which engages with a locking element of the joining member (6) when the three parts (1, 2, 3) are joined, so as to move the device (4) rearward into a position (B) wherein the springs (5) exert a forward return force on the locking device. Retaining means inside the device (4) allow locking of the device in the second position and clamping of an intermediate part (2) between the front part (3) and the rear part (1).
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: January 13, 2009
    Assignee: Bull SAS
    Inventors: Lionel Coutancier, Sebastien Magnoux
  • Patent number: 7475165
    Abstract: Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: January 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kinji Mitani, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
  • Patent number: 7474584
    Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: January 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Koichiro Ishibashi, Shigezumi Matsui, Kenichi Osada
  • Patent number: 7469810
    Abstract: Staple magazine (7) for mounting to a stapler (1) used to staple together a workpiece (6), primarily a sheaf of papers, the said staple magazine comprising a container (8), in which elongated staple blanks (10) in the form of a strip (11) are stored, and a staple forming arrangement (9) comprising a forming punch (19), which bends the elongated staple blanks into the shape of a staple over a forming block (48), and a drive punch (20) with which the staple blanks which have been bent into staple shape for stapling the workpiece are driven into the said workpiece, the staple blanks stored in strip form being fed by a feeder plate (51) to a forming block (48) along a feed path (44) incorporated in the container, and the forming punch and drive punch being driven in a reciprocating bending and drive movement (P) by a drive arrangement (13-16) incorporated in the stapler, the container (8) and the staple forming arrangement (9) being connected to each other by means of releasable connecting devices (22, 23, 34, 35
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: December 30, 2008
    Assignee: Isaberg Rapid AB
    Inventors: Olle Strååt, Marcus Börjesson
  • Patent number: 7469963
    Abstract: An orthopedic back support for displacing a person's weight from the lower area of the spine by providing support for the upper torso and for use with a chair or seat having a seat base and a seat back. A flexible fabric cross piece is connected between vertical members to provide back support. The cross piece may include vertical channels or sleeves at opposite sides to receive and support the vertical members. A flexible strap is connected to the fabric or the vertical members and adapted to be positioned behind a seat or a head rest. The entire unit is portable or may be fabricated as part of a seat.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 30, 2008
    Inventor: John G. Rutty
  • Patent number: 7470568
    Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 30, 2008
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Shinji Tojo, Shinya Kanamitsu, Seiichi Ichihara
  • Patent number: 7470355
    Abstract: A process for electrochemically reducing a metal oxide, such as titania, in a solid state in an electrochemical cell that includes a bath of molten electrolyte, a cathode, and an anode, which process includes the steps of: a) applying a cell potential across the anode and the cathode that is capable of electrochemically reducing the metal oxide supplied to the molten electrolyte bath, b) continuously or semi-continuously feeding the metal oxide in powder and/or pellet form into the molten electrolyte bath, c) transporting the powders and/or pellets along a path within the molten electrolyte bath and reducing the metal oxide as the metal oxide powders and/or pellets move along the path, and d) continuously or semi-continuously removing metal from the molten electrolyte bath. Also disclosed and claims is an electrochemical cell for carrying out this process.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: December 30, 2008
    Assignee: BHP Billiton Innovation Pty Ltd
    Inventors: Steve Osborn, Ivan Ratchev, Les Strezov, Greg Rigby
  • Patent number: 7470180
    Abstract: A rock trap disposed in a feeder adapter of a combine directly behind a sickle bar of a combine header and in an area in front of a rearwardly directed conveyor located for receiving cut crop from transversely directed conveyor of the header. The rock trap has a trap door which can be selectively opened so as to drop beneath the header rocks collected therein.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 30, 2008
    Assignee: Honey Bee Manufacturing Ltd.
    Inventor: Gregory J. Honey
  • Patent number: 7471563
    Abstract: Suppressing a leakage current is required in a flash memory because the channel length is made shorter with a reduction in the memory cell size. In an AND type memory array having an assist electrode, although the memory cell area has been reduced by the field isolation using a MOS transistor, leakage current in the channel direction becomes greater with a reduction in the memory cell size, resulting in problems arising like deterioration of programming characteristics, an increase in the current consumption, and reading failure. To achieve the objective, in the present invention, electrical isolation is performed by controlling at least one assist electrode of the assist electrodes wired in parallel to be a negative voltage during program and read operations and by making the semiconductor substrate surface in the vicinity of the aforementioned assist electrode non-conductive.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 30, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hideaki Kurata, Kazuo Otsuga, Yoshitaka Sasago, Takashi Kobayashi, Tsuyoshi Arigane
  • Patent number: 7468901
    Abstract: In a two-transistor gain cell structure, a semiconductor memory device capable of stable reading without malfunction and having small-area memory cells is provided. In a two-transistor gain cell memory having a write transistor and a read transistor, a write word line, a read word line, a write bit line, and a read bit line are separately provided, and voltages to be applied are independently set. Furthermore, a memory cell is connected to the same read word line and write bit line as those of an adjacent memory cell.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: December 23, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Norifumi Kameshiro, Riichiro Takemura, Tomoyuki Ishii
  • Patent number: 7468913
    Abstract: A highly-reliable semiconductor device is realized. For example, each memory cell of a nonvolatile memory included in the semiconductor device is configured to include a source and a drain formed in a P-well, a memory node which is formed on the P-well between the source and the drain via a tunnel insulator and is insulated from its periphery, and a control gate formed on the memory node via an interlayer insulator. When a programming operation using channel hot electrons is to be performed in such a configuration, the P-well is put into an electrically floating state.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: December 23, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tetsufumi Kawamura, Hitoshi Kume, Tsuyoshi Arigane
  • Patent number: 7467339
    Abstract: A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: December 16, 2008
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Masahiko Kimura, Isao Nakamura
  • Patent number: 7460396
    Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: December 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yasushi Oka, Kazuyoshi Shiba
  • Patent number: 7459803
    Abstract: An Iso-Parallel UPS system may combine the system redundancy, isolation and fault-limiting properties of isolated-redundant systems, with the ability to spread system load evenly across all modules like paralleled systems. This system may have the following features: (1) the critical load can be divided into two or more portions, and each portion may be individually fault tolerant, i.e., any electrical fault on a critical load will affect only the load in that portion—other portions of the critical load can remain connected and operating; (2) the critical load can be shared among all modules within the configuration, and all modules may be equally loaded, or nearly equally loaded—there is no designated redundant unit; and (3) any module can be taken out for maintenance without impacting the critical load.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: December 2, 2008
    Assignee: Isolated Parallel Inc.
    Inventor: Michael J. Mosman
  • Patent number: D581464
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: November 25, 2008
    Assignee: BMT Designers & Planners, Inc.
    Inventor: Mike Hicks
  • Patent number: D581766
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 2, 2008
    Assignee: Isaberg Rapid AB
    Inventors: Marcus Heneen, Daniel Höglund