Abstract: Current consumption in a nonvolatile memory apparatus operable on two or more different power voltages is to be substantially reduced in its standby mode. A stepped-down power supply unit provided in a flash memory to generate an internal power voltage, when supplied from outside with about 3.3 V as a power voltage, causes a first stepped-down power supply circuit to output the internal power voltage to control circuits when in normal operation. In a low power consumption mode, a second stepped-down power supply circuit outputs the internal power voltage to the control circuits, and in a standby mode a third stepped-down power supply circuit outputs to the control circuits an internal power voltage stepped down by an N-channel MOS transistor.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: The common zoom optical system is provided that is almost commonly used in a plurality of zoom lenses as a component and that is capable of suppressing fluctuation in aberrations and deviation in the position of the image plane, wherein the common zoom optical system is almost commonly used in a plurality of zoom lenses as a component, and when zooming from a wide-angle end state of a plurality of the zoom lenses composed by use of the common zoom optical system to a telephoto end state thereof, a moving path of the common zoom optical system differs for each zoom lens.

Abstract: An orthopedic back support for displacing a person's weight from the lower area of the spine by providing support for the upper torso and for use with a chair or seat having a seat base and a seat back. A flexible fabric cross piece is connected between vertical members to provide back support. The cross piece may include vertical channels or sleeves at opposite sides to receive and support the vertical members. A flexible strap is connected to the fabric or the vertical members and adapted to be positioned behind a seat or a head rest. The entire unit is portable or may be fabricated as part of a seat.

Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.

Abstract: The invention is a laboratory mill that allows small samples to be shaken, mixed, ground, homogenized or comminuted effectively within a small vial. The design is similar to a planetary mill but unlike those devices, neither axis of rotation is centered on the axis of the processing vessel. The design allows many vials to be processed at one time and even when the diameter of the vial is quite small, maintains the processing performance. The performance of the device when used as a comminuter is demonstrated showing that the device can comminute organic solids down to a median particle size of 1 micrometer with a narrow size distribution. Because the processing takes place within a vial, the mill does not require cleaning between samples which allows the application of the device in automated or high throughput systems.

Abstract: Flash memory is rapidly decreasing in price. There is a demand for a new memory system that permits size reduction and suits multiple-value memory. A flash memory of AND type suitable for multiple-value memory with multiple-level threshold values can be made small in area if the inversion layer is utilized as the wiring; however, it suffers the disadvantage of greatly varying in writing characteristics from cell to cell. Another promising method of realizing multiple-value memory is to change the storage locations. This method, however, poses a problem with disturbance at the time of operation. The present invention provides one way to realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics.

Abstract: A risk of data garbling due to cumulative impact of disturbances occurring in memory areas in which no rewrite occurs is to be prevented. A memory device has an erasable and writable nonvolatile memory and a control circuit, wherein the control circuit is enabled to perform processing at a prescribed timing to replace memory areas. The replacement processing is accomplished by writing stored data in a first memory area in which rewriting is relatively infrequent into an unused second memory area, and making the second memory area into which the writing has been done a used area in place of the first memory area. Since this replacement processing is intended to replace memory areas in which rewriting is infrequent with other memory areas as described above, it is possible to prevent the risk of data garbling due to the cumulative impact of disturbances occurring in memory areas in which no rewrite occurs.

Abstract: A plasma display panel and an imaging device realize a high luminous efficiency, a long lifetime and stable driving. The plasma display panel uses a discharge-gas mixture containing at least Xe, Ne and He. A Xe proportion of the discharge-gas mixture is in a range of from 2% to 20%, a He proportion of the discharge-gas mixture is in a range of from 15% to 50%, the He proportion is greater than the Xe proportion, and a total pressure of the discharge-gas mixture is in a range of from 400 Torr to 550 Torr. A width of a voltage pulse to be applied to an electrode serving as an address electrode is 2 ?s or less.

Abstract: A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.

Abstract: To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is added to the instruction code, are supplied to the thread multiplexer. The issue information is valid from the second and subsequent instruction flows, and is saved temporarily in an issue information buffer. This issue information is for example the position of an operating cycle which can issue a high priority instruction, i.e., information showing a slot. The thread multiplexer issues a low priority instruction at another operating cycle at which a high priority instruction is not issued according to the issue information.

Abstract: A microcomputer capable of reducing a board area, enhancing the security, and improving the usability is provided. A microcomputer to be used in a notebook PC is disclosed, in which programs of a keyboard/power management BIOS and a system BIOS are stored in a built-in flash memory ROM. In order to set read (R)/write (W) protect to the BIOSes stored in the flash memory ROM, a read/write protect setting register is provided, and at initial setting after the release of reset, flags of R/W permission, R permission/W prohibition, W permission/R prohibition, and R/W prohibition are set to this register by a central processing unit CPU. By doing so, it becomes possible to achieve protection such as the prevention of error writing of the BIOS and the like between a host machine and the flash memory ROM via a LPC bus.

Abstract: An electrically-driven steering column apparatus includes a steering column rotatably holding a steering shaft and capable of adjusting a position of the steering wheel, and a power transmission mechanism for transmitting to the steering column a rotational driving force of an electric motor as a position adjusting motion driving force, wherein the power transmission mechanism has a joint constructed of a spherical joint element and a cylindrical joint element in which the spherical joint element is slidably fitted, on within a driving force transmission route.

Abstract: A zoom lens system having higher optical performance, a wide angle of view, a high zoom ratio, and compactness include, in order from an object, a first group having negative power, a second group having positive power, and a third group having positive power. At least the first and second lens groups are moved upon zooming. The first group has, in order from the object, a negative meniscus lens having a convex surface facing the object, and a positive lens. At least one surface of the negative meniscus lens is an aspherical surface. The second group has, in order from the object, a first positive lens, a second positive lens, a negative lens, and a third positive lens. At least one surface of the first positive lens is an aspherical surface. The third group has one positive lens, and at least one surface thereof is an aspherical surface.

Abstract: An impact absorption type steering column apparatus for a vehicle is constructed such that a steering column is moved forwardly of the vehicle with respect to a car body sided member when a secondary collision happens. An outer peripheral surface of the steering column is fitted with a metallic ring that engages with the car body sided member to absorb impact energy while frictionally sliding on the steering column moving forwardly of the vehicle, when the secondary collision happens.

Abstract: A microprocessor used in a pair with a baseband processor for performing the baseband processing, is provided with a central processing unit for calculation processing, a counter capable of measuring time in the calculation processing by the central processing unit, and an interface which enables the baseband processor to read the counter. By making the baseband processor read the counter, the processing by the baseband processor is synchronized with the processing by the central processing unit in the microprocessor. Consequently, it is possible to establish synchronization between video and voice when the video processing and the voice processing are separately performed by different processors.

Abstract: A semiconductor integrated circuit is provided with an external interface circuit, which includes a clock generation circuit for generating a synchronous clock signal to establish synchronization between data input and output through input and output of a data string sectioned at fixed intervals. The clock generation circuit includes a self-excited oscillator circuit serving as an oscillation source for the synchronous clock signal, and a control circuit for trimming the oscillation frequency of the self-excited oscillator circuit. The control circuit detects the sections made at the fixed intervals to the data string, measures the section interval based on an oscillation output of the self-excited oscillator circuit, and controls the oscillation frequency of the self-excited oscillator circuit to match the measurement value to a target value.

Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

Abstract: Disclosed herewith is a semiconductor data processing device that realizes low power consumption at the standby time and at the operation time, as well as speeds up the interfacing operation. The semiconductor data processing device can connect a non-volatile storage device to a general-purpose bus of a host system. The data processing device enters the active or standby state in response to the state of the general-purpose bus. In the standby state, the data processing device stops the internal clock signal and applies a substrate bias voltage to each object so as to suppress the potential sub-threshold leak current therefrom. This bias voltage is also applied to the central processing unit and the rewritable non-volatile memory for storing a control program to be executed by the central processing unit. The central processing unit processes data in units of n bits or below when the interface controller and the data transfer controller input/output parallel data in units of 2n bits.