Abstract: In order to protect the user security data, provided is a memory card capable of preventing the data leakage to a third party not having the access authority by imposing the limitation on the number of password authentications and automatically erasing the data. In a system comprised of a multimedia card and a host machine electrically connected to the multimedia card and controlling the operations of the multimedia card, a retry counter for storing the number of password authentication failures is provided and the upper limit of the number of failures is registered in a register. When passwords are repeatedly entered once, twice, . . . and n times and the retry counter which counts the entries reaches the upper limit of the number of failures, the data is automatically erased so as not to leave the data in the flash memory.

Abstract: According to the present invention, a rolling element 7 for rotating upon relative movement of both shafts 1 and 2 in the axial direction is disposed between three pairs of axial grooves 3 and 5 which are formed on the outer peripheral surface of the male shaft 1 and on the inner peripheral surface of the female shaft 2, respectively, a raceway surface element 9 which is in contact with the rolling element 7 and an elastic member 10 for pressurizing the rolling element 7 against the male shaft 1 and the female shaft 2 through the raceway surface element 9 are interposed between the axial groove 3 on the male shaft side 1 and the rolling element 7, and a sliding member 8 for slidably moving upon relative movement of the both shafts 1 and 2 in the axial direction is disposed between another three pairs of axial grooves 4 and 6 which are formed on the outer peripheral surface of the male shaft 1 and on the inner peripheral surface of the female shaft 2, respectively.

Abstract: A data processor arranged so that a block transfer control unit (12) can initiate block transfer in response to the execution of a particular instruction by a CPU, in order to increase the speed and efficiency of the data transfer between a CPU-accessible internal memory (5) and an external memory (25,26). When an address specified by the addressing field coincides with an address mapped to the internal memory, the particular instruction sets a logical address as one of the transfer source or transfer destination addresses of the data block transfer. The internal memory is allotted to a part of virtual address space; the internal memory allotted so is associated with the physical address space, to which the external memory set as the other address is allotted, by a process in which a TLB is used when the MMU is in ON, and a given register is used when the MMU is in OFF.

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: The present invention provides a process for producing a polycrystal silicon film which comprises a step of forming a polycrystal silicon film by light irradiation of a silicon film set on a substrate, and a step of selecting substrate samples having an average grain size in a plane of the sample of 500 nm or more. According to the present invention, stable production of a high-performance poly-silicon TFT liquid crystal display becomes possible.

Abstract: There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respective columns of the memory cells. Further, the dummy cells are disposed for the respective columns of the memory cells. The dummy cells are each made up of a series-circuit including a first switching transistor that is turned into the conducting state in response to a signal potential on a dummy word line (DWL), and a second switching transistor 17 for coupling an adjacent source line to the bit line corresponding thereto in response to a potential of the source line in a column corresponding thereto. The memory cells each are made up of one unit of a transistor and a data storage formed by mask wiring.

Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ? of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: The disclosed invention is intended to decrease the power consumption of a pulse latch circuit. A pulse latch circuit that operates in sync with a pulsed clock signal, including a first operation mode in which shifting test pattern scan data is performed and a second operation mode in which shifting the test pattern scan data is not performed, comprises the following circuits: a first latch circuit that is able to latch input data in sync with the clock signal; a second latch circuit that is connected to the first latch circuit and is able to latch the test pattern scan data to be shifted in sync with the clock signal; and a control circuit that stops supply of the clock signal to the second latch circuit during the second operation mode. By thus stopping the supply of the clock signal to the second latch circuit, decrease the power consumption is achieved.

Abstract: In a motor-driven steering wheel position adjustment apparatus, a nut 17 being a driven member is mounted such that it can be detached from an inner column of a steering column, based on a shock load applied at the time of a secondary collision, and therefore a threaded rod of a feed screw mechanism does not have resistance with respect to displacement of the inner column in the forward direction at that time. Improvement in the protection of a driver at the time of a collision can thus be achieved, and, since an integrated member can be used for the threaded rod, silence during the position adjustment of a steering wheel by the feed screw mechanism can be ensured.

Abstract: A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads.

Abstract: The purpose is to provide a large-aperture-ratio internal focusing telephoto lens applicable to a wider photographing area by equipping a vibration reduction function capable to satisfactorily correct a camera shake and the like with securing superb optical performance. The large-aperture-ratio internal focusing telephoto lens includes, in order from an object, a first lens group G1 having positive refractive power, a second lens group G2 having negative refractive power, and a third lens group G3 having positive refractive power. The second lens group G2 is moved along an optical axis upon changing focus from infinity to a close-range object. The first lens group G1 has at least two cemented lenses and satisfies a given conditional expression. Either one of the cemented lens satisfies a given conditional expression.

Abstract: The invention relates to an arm exoskeleton comprising a moving system of joints placed in parallel with the joints of the human arm, the exoskeleton comprising a shoulder exoskeleton, an elbow exoskeleton, and a wrist exoskeleton. In all, the exoskeleton has sixteen joints providing sixteen degrees of freedom. A support worn on the torso of a human operator comprises a rigid front plate and a rigid back plate. The shoulder exoskeleton has its proximal end fixed to the front plate, whereby the front plate provides a fixed reference for all movements of the exoskeleton, and the wrist exoskeleton is fixed to a rigid glove worn on the hand of the operator. Active joints are controlled by flexible cable tendons bridging the exoskeleton, said tendons themselves being actuated by control units disposed on the rigid back plate. Inflatable cushions prevent the wrist exoskeleton and the shoulder exoskeleton from moving relative to the arm of the operator.

Abstract: The object of the present invention is to provide a new nonvolatile semiconductor memory device and its manufacturing method for the purpose of miniaturizing a virtual grounding type memory cell based on a three-layer polysilicon gate, enhancing the performance, and boosting the yield. In a memory cell according to the present invention, a floating gate's two end faces perpendicular to a word line and channel are partly placed over the top of a third gate via a dielectric film. The present invention can reduce the memory cell area of a nonvolatile semiconductor memory device, increase the operating speed, and enhances the yield.

Abstract: A method for improving productivity when manufacturing a semiconductor device. A lower electrode, insulating films, an upper electrode and insulating films are formed on a semiconductor substrate in a sensor region. A cavity is formed between the insulator films above the lower electrode. The lower electrode, insulating film, the cavity and insulating film, and an upper electrode form a variable capacity sensor. The cavity is formed by etching a sacrificial pattern between the insulation films by way of a hole formed in a pair of insulation films. Other than in the above sensor region, a dummy lower electrode and four insulating films are formed on the TEG region on the semiconductor substrate; and a dummy cavity is formed between a pair of insulation films above the lower electrode however no conductive layer on the same layer as the upper electrode is formed on the dummy cavity.

Abstract: For use in an amplifier configuration including a high-power amplifier and a low-power amplifier which are always interconnected in terms of high frequencies and between which switching is made using no switches, a highly stable high-frequency power amplifier module with high isolation between the amplifiers is provided. To reduce wrapping around from a low-power amplifier section in an activated state to a high-power amplifier section in a deactivated state or from the high-power amplifier section in an activated state to the low-power amplifier section in a deactivated state, an input matching circuit having high isolation characteristics is included in an input matching circuit portion which does not have much to do with amplifier efficiency. Switching of each of the amplifier sections between an activated state and a deactivated state is effected by control using bias input terminals.

Abstract: The present invention provides a film bulk acoustic wave resonator (FBAR) filter that can keep the Q factor high. The FBAR filter comprises a first FBAR with a first resonant frequency and a second FBAR with a second resonant frequency, formed on a same substrate. The FBAR filter has such a structure that a first underlayer is formed between the substrate and a first bottom electrode layer and a second underlayer is formed between the substrate and a second bottom electrode layer, the first underlayer thickness being different from the second underlayer thickness.

Abstract: A liquid crystal drive device having a differential-type input circuit including a differential amplification stage for receiving a differential signal and a buffer stage for generating an output signal on the basis of an output of the differential amplification stage, the liquid crystal drive device for receiving a signal of display data via the input circuit and outputting a signal for driving a liquid crystal panel on the basis of the display data, wherein a liquid crystal driving voltage VLCD larger than a power supply voltage VCC for logic to be supplied to the operation voltage buffer stage is supplied to the differential amplification stage of the input circuit. A standby function of interrupting an operation current of the differential amplification stage in a period where no display data is received is provided.

Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.