Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7401585
    Abstract: In a vehicle starter apparatus incorporating therein a starting motor and a one-way clutch, a damper for mitigating vibration of an engine is disposed at a position between the one-way clutch and the engine, and at the same time, between the engine and a transmission.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 22, 2008
    Assignee: NSK-Warner K.K.
    Inventor: Hirobumi Shirataki
  • Patent number: 7403408
    Abstract: A semiconductor memory device that satisfies needs of both a large number of memory banks and a higher operation speed is provided. A semiconductor memory device includes a plurality of data terminal pads, and a plurality of memory banks independently subject to memory access. Each of the memory banks is divided into a plurality of submemory banks. The data terminal pads are also divided into a plurality of groups so as to be associated with submemory banks obtained by the division. Blocks each including submemory banks obtained by the division and data terminal pads associated with the submemory banks are arranged so as not to overlap each other on a semiconductor chip.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 22, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Otori, Masatoshi Hasegawa, Mitsugu Kusunoki, Masatoshi Sakamoto
  • Patent number: 7399694
    Abstract: By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is achieved.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 15, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Michiaki Sugiyama, Hiroshi Kawakukbo
  • Patent number: 7401257
    Abstract: There are provided a central processing unit (2), a high-speed serial communication interface circuit which can be utilized for a debugging interface, for example, a USB interface circuit (3), and an external bus interface circuit (5) which can be connected to an external memory. The USB interface circuit has a plurality of input buffers (EP 1, EP 2) therein and data can be output from one of the input buffers in parallel with an input operation to the other input buffer. In a debugging mode, the USB interface circuit receives a system program, and the system program thus received can be output from the external bus interface circuit together with a memory access control signal. When a target program is to be downloaded from a host computer into a target system, a speed of a data transfer can be increased.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: July 15, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Kazuo Usui
  • Patent number: 7397693
    Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd? higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
  • Patent number: 7397879
    Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Takeshi Sakata, Takashi Sato
  • Patent number: 7398378
    Abstract: In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Sugure, Kenta Morishima
  • Patent number: 7397878
    Abstract: The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Okuda, Takeshi Sakata, Takashi Sato
  • Patent number: 7398406
    Abstract: It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takanobu Naruse, Hirokatsu Noguchi, Kazuhide Kawade, Yoshiyuki Matsumoto
  • Patent number: 7394143
    Abstract: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Satoshi Umekita, Tomomi Ajioka, Kenji Hirose, Yoshihiko Yasu, Yujiro Miyairi
  • Patent number: 7393282
    Abstract: A coupling structure for coupling a pair of steering torque transmitting members interposed in a steering shaft is arranged such that a steering torque is transmitted from one of the steering torque transmitting members to the other through a pin. One of the steering torque transmitting members has a pin insertion hole formed with a large diameter hole portion, a stepped receiving portion and a small diameter hole portion, while the pin has a large diameter portion, a stepped portion and a small diameter portion which are respectively engaged with the large diameter hole portion, the stepped receiving portion and the small diameter hole portion of the pin insertion hole.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: July 1, 2008
    Assignee: NSK Ltd.
    Inventors: Kazunori Takahashi, Seiichi Tachikawa
  • Patent number: 7393737
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: July 1, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 7391354
    Abstract: One input terminals of switches respectively coupled to capacitors of a capacitance array type D/A converter configured as a main DAC are coupled to a first external terminal of an IC. On the other hand, a current switching type D/A converter of a resistance string type D/A converter configured as a sub DAC that causes a DC current to flow therethrough is coupled to a second external terminal of the IC.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: June 24, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hiroyuki Tsunakawa, Akihiro Kitagawa
  • Patent number: 7391083
    Abstract: A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: June 24, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kunihiko Kato, Masami Koketsu, Shigeya Toyokawa, Keiichi Yoshizumi, Hideki Yasuoka, Yasuhiro Takeda
  • Patent number: 7389881
    Abstract: A method of recovering a valuable component from a feed slurry in minerals processing plant for a mined material is disclosed. The method includes separating the feed slurry on the basis of particle size into at least two streams, of which one stream is a fines stream. The pH of the fines stream is then adjusted to be within a range in which contaminants on the surface of the fines are soluble so that contaminants dissolve from the surface of the fines. Thereafter, the valuable component is floated from the pH adjusted fines stream.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: June 24, 2008
    Assignee: BHP Billiton Pty Ltd
    Inventors: John Patrick Andreatidis, Christofo Torrisi
  • Patent number: 7385853
    Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 10, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masaaki Terasawa, Yoshiki Kawajiri, Takanori Yamazoe
  • Patent number: 7383932
    Abstract: A clutch hub provided with a side wall at an end of a cylindrical portion. The cylindrical portion is formed to have convexed and concaved portions to serve as a spline and an oil passage is formed on a tooth of the spline. An oil dam is formed by plastic deformation on the inner peripheral surface of the tooth of the spline with the oil passage formed thereon at a position separated from an open end by a predetermined distance, concaved grooves are formed on the outer peripheral surface of the spline with the oil dam formed thereon.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: June 10, 2008
    Assignee: NSK-Warner K.K.
    Inventors: Tomoyuki Miyazaki, Kiyokazu Ichikawa, Yosuke Ikeda
  • Patent number: 7384820
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Patent number: 7385870
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corp., SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Patent number: D573343
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: July 22, 2008
    Assignee: Gamewear, Inc.
    Inventor: Frank Cerullo