Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 7290795
    Abstract: A garnish clip comprises a body attachment portion for attachment to a vehicle body and a garnish attachment portion for attachment to a garnish. The garnish attachment portion comprises a plate-shaped base with one end connected to the body attachment portion and a plate-shaped garnish engagement portion connected to the other end of the base by a U-shaped connection. The garnish engagement portion and the base are also connected by a thin breakable connector near the body attachment portion. Ribs on the garnish attachment portion provide rigidity to limit opening of the garnish engagement portion away from the body attachment portion when the airbag deploys and the thin connector breaks due to collision or roll-over forces.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: November 6, 2007
    Assignee: Newfrey LLC
    Inventors: Yasuhiro Kawai, Koya Teshima
  • Patent number: 7290097
    Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: October 30, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hirofumi Shibuya, Fumio Hara, Hiroyuki Goto, Shigemasa Shiota
  • Patent number: 7290124
    Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: October 30, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Sugure, Tomomi Ishikura, Kazuya Hirayanagi, Takeshi Kataoka, Seiji Takeuchi, Hiromichi Yamada, Takanaga Yamazaki
  • Patent number: 7286386
    Abstract: A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Miwa, Yasumi Tsutsumi, Masahiro Ichitani, Takanori Hashizume, Masamichi Sato, Naozumi Morino, Atsushi Nakamura, Saneaki Tamaki, Ikuo Kudo
  • Patent number: 7283408
    Abstract: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: October 16, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tsutomu Nakajima, Satoshi Noda, Kenji Kozakai, Atsushi Tokairin
  • Patent number: 7282377
    Abstract: In the manufacturing process of a semiconductor integrated circuit device, a plurality of identification elements having the same arrangement are formed and the relation of magnitude in a physical amount corresponding to variations in the process of the plurality of identification elements is employed as identification information unique to the semiconductor integrated circuit device.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 16, 2007
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventor: Masaya Muranaka
  • Patent number: 7280104
    Abstract: It is aimed at being capable of easily changing a power supply startup procedure and complying with various display devices. A power supply circuit is provided between an instruction register of a liquid crystal driver and a power supply unit. The power supply unit is not directly supplied with a setting value registered to the instruction register from a microprocessor unit. The microprocessor unit writes setting values to the instruction register without need for the time axis. To turn on the power, the time is measured inside the power supply sequencer. Set values are sequentially input to the power supply unit. The instruction register should be also capable of registering an input timing.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shin Morita, Goro Sakamaki, Toshikazu Tachibana
  • Patent number: 7280416
    Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: October 9, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
  • Patent number: 7277037
    Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 2, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yada, Yasuyuki Saito
  • Patent number: 7277038
    Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 2, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Yada, Yasuyuki Saito
  • Patent number: 7277039
    Abstract: A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 2, 2007
    Assignee: Rensas Technology Corp.
    Inventors: Naoki Yada, Yasuyuki Saito
  • Patent number: 7275618
    Abstract: To provide an electrically driven power steering apparatus with a simple structure, which can prevent overloading of an electrical motor and a power transmission system, an absorbing member (121) is attached to a rack shaft (112), and is brought into contact with a rack housing face at a stroke end of the rack shaft (112). The absorbing member (121) at least partially has a material having a Young's modulus of 100 to 900 Mpa, and thus it is possible to effectively relieve an impact at the stroke end.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: October 2, 2007
    Assignee: NSK Ltd.
    Inventors: Manabu Abe, Kazuo Chikaraishi, Atsushi Tanaka
  • Patent number: 7275262
    Abstract: A method for providing secure communication between first and second systems connected to the internet includes assigning respective permanent internet addresses to first and second entities associated with the systems, making at least one application located in a server of said second system accessible to the first entity, and encrypting data exchanged between the first and second entities in conformity with a desired security protocol. The first and second systems each include a communication protocol stack having at least one layer which allows for the encrypting step to be performed. Through this method, a user in the first system can directly address an application hosted by the second system without using or even knowing the name of the host system. The entity in the first system may be a wireless unit operating, for example, in GSM and the entity in the second system may be a server in an intranet.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: September 25, 2007
    Assignee: Bull S.A.
    Inventor: Michel Habert
  • Patent number: 7273227
    Abstract: A clip for attaching a curtain-shield airbag to a body panel of a vehicle comprises a bushing and a pin. The bushing has a flange with a leg extending therefrom. A bore extends through the flange and into the leg for receiving the pin. Outer surfaces of the leg have engagement pieces with shoulders for coupling the bushing to edge regions of a body panel hole into which the leg is inserted. The pin and the bushing are capable of being coupled in a provisionally fixed condition or a permanently fixed condition. When the pin is partially inserted into the bore, the engagement pieces are permitted to flex inwardly of the bore, but when the pin is fully inserted, such inward flexing is prevented. The flange has a wall that provides a partition between the main airbag unit and the entrance hole of the bore in the flange.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: September 25, 2007
    Assignees: Newfrey LLC, Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Yasuhiro Kawai, Yasushi Kubota, Tatsuya Goto, Hirokazu Niimi
  • Patent number: 7273338
    Abstract: A blind rivet and a method of assembly comprising a tubular shell and mandrel in combination. The mandrel comprises a stem and a radially-enlarged head which in use forms a blind head to the shell to set the rivet, in which either the head of the mandrel or the bore of the shell is formed with a plurality of depressions the bases of which lie on a notional circle having a diameter which, where the depressions are formed in the head of the mandrel, is less than the bore of the shell or, where the depressions are formed in the bore of the shell, is greater than the diameter of the head of the mandrel. The depressions, which are preferably generally longitudinally disposed, define ribs, ridges or other protusions therebetween which in use and on pulling the mandrel into the shell bore extend radially beyond the bore of the shell, so that material of the shell becomes displaced by contact with the ridges and occupies the depressions. The invention may be applied either to pull-through, or self-plugging rivets.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: September 25, 2007
    Assignee: Milladale Limited
    Inventor: Frederick Arthur Summerlin
  • Patent number: 7275132
    Abstract: The computing machine (1) comprises a RAM (3) and a mass memory (5) in which an operating system is stored. The mass memory (5) comprises a partition (8) that is read-only accessible to the operating system, said partition (8) containing a startup function, an automatic repair function, and a function for mounting said operating system.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: September 25, 2007
    Assignee: Bull SA
    Inventors: François Cunchon, Van-Dung Nguyen, Michael Planes
  • Patent number: 7271475
    Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 18, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tamaki Wada, Hirotaka Nishizawa, Masachika Masuda, Kenji Osawa, Junichiro Osako, Satoshi Hatakeyama, Haruji Ishihara, Kazuo Yoshizaki, Kazunori Furusawa
  • Patent number: 7269748
    Abstract: Disclosed herewith is a semiconductor processing system such as a card type electronic device, which can easily cope with an error caused by power shutoff that occurs when the card is ejected. The semiconductor processing system is provided with an interface control circuit and a processing circuit and receives operation power from an external device such as a card slot when it is inserted therein. According to a first aspect of the present invention for coping with an error caused by power shutoff that occurs when the card is ejected, the interface control circuit, when the card is ejected from the card slot, detects a potential change to occur at a first external terminal to be disconnected from a predetermined terminal of the card slot before the power supply from the card slot is shut off, then instructs the processing circuit that is active to perform an ending processing. The semiconductor processing system can end the processing by itself before the power supply stops completely.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Shinichi Shuto, Takayuki Tamura, Chiaki Kumahara
  • Patent number: 7267287
    Abstract: An IC card capable of reinforcing the prevention of the electrostatic damage without causing a rise in the cost of a semiconductor integrated circuit chip. The semiconductor integrated circuit chip (2) is mounted on a card substrate (1), and plural connection terminals (3) are exposed. The connection terminals are connected to predetermined external terminals (4) of the semiconductor integrated circuit chip, first overvoltage protection elements (7, 8, 9) connected to the external terminals are integrated in the semiconductor integrated circuit chip, and second overvoltage protection elements such as surface-mount type varistors (11) connected to the connection terminals are mounted on the card substrate. The varistors are variable resistor elements having a current tolerating ability greater than that of the first overvoltage protection elements.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: September 11, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Nishizawa, Yosuke Yukawa, Takashi Totsuka
  • Patent number: D552658
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: October 9, 2007
    Assignee: Cross Winds Concepts, LLC
    Inventors: Darrin Moore, John Buchanan, Edward J. Kondracki