Abstract: A semiconductor laser element capable of reducing the contact resistance and the thermal resistance and realizing a high reliability is provided. The semiconductor laser element includes: a semiconductor substrate, an active layer formed on the semiconductor substrate, a ridge having a clad layer formed on the active layer and a contact layer formed on the clad layer, an insulation film covering the side surfaces of the clad layer, and an electrode connected to the contact layer, wherein the insulation layer has an end portion in the ridge thickness direction located between the upper surface and the lower surface of the contact layer.

Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.

Abstract: The present invention provides a memory card equipped with an interface controller connected to external connecting terminals, a memory connected to the interface controller, and a security controller connected to the interface controller. A second external connecting terminal capable of supplying an operating power supply to the security controller is provided aside from a first external connecting terminal which supplies an operating power supply to the interface controller and the memory. An interface unit of the interface controller connected to the security controller receives the operating power supply from the second external connecting terminal and thereby enables a stop of the supply of the operating power supply from the first external connecting terminal. Even if the supply of the operating power supply to the interface controller is cut off, the output of the interface unit is not brought to an indefinite state.

Abstract: A method for controlling the communications of a computer in a computer network or a plurality of single computers in a computer network, in which the computer is connected to other computers and the single computers are connected with each other via a standard network LAN and a high performance network SAN. Each single computer comprises, in an operation system kernel, a protocol unit connected with the standard network LAN for servicing communication protocols and a library, which is connected in front of the operation system kernel, for which applications are sitting at a communication interface. Selection of the communication path between the standard network LAN and the high performance network SAN occurs in a network selection unit integrated with a base library. It is thereby provided that the network selection happens after the communication interface of the library and before access to the operation system kernel.

Abstract: Under the condition that a semiconductor maker and a photomask maker are separated but these are mutually connected with a communication line, the semiconductor maker gives a photomask fabrication schedule information to the photomask maker via the communication line, while the photomask maker fabricates the photomask depending on such fabrication schedule information and delivers the photomask to the semiconductor maker. The photomask maker periodically sends, in the course of fabrication process, a photomask fabrication progress information to the semiconductor maker via the communication line. The semiconductor maker regenerates the photomask fabrication schedule information depending on the photomask fabrication progress information sent from the photomask maker and then transfers the re-generated photomask fabrication schedule information to the photomask maker via the communication line.

Abstract: To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.

Abstract: An IC card has a card substrate having semiconductor integrated circuit chips mounted thereon and a plurality of connector terminals formed thereon. The connector terminals are exposed from a casing. The connector terminals are laid out in plural sequences in staggered form between sequences adjacent to one another forward and backward as viewed in an IC card inserting direction. Owing to the adoption of the staggered layout, a structure or configuration wherein the amounts of protrusions of socket terminals of a card socket are changed and the socket terminals are laid out in tandem, can be adopted with relative ease. If a connector terminal arrangement of a downward or low-order IC card is adopted as a specific connector terminal sequence as it is, whereas a function dedicated for an upward or high-order IC card is assigned to another staggered connector terminal arrangement, then backward compatibility can also be implemented with ease.

Abstract: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.

Abstract: A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

Abstract: A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank) 1 to 3 where the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CD0 and CD1, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #2, the data of Bank 2 stored in CD1, Row 2 cannot be written back since Bank 2 is busy with the cycle #1, the data of Bank 0 stored in CD 0, Row 2 can be written back instead.

Abstract: The present invention concerns a method for generating nanostructures in order to obtain in an area on the surface of a metal piece (10) a nanostructured layer of defined thickness, characterized in that it comprises: a step for projecting onto an impact point in the area of the surface of the piece (10) to be treated, for a given duration, at a given speed and at variable incidences at the same impact point, a given quantity of perfectly spherical balls (22) of given dimensions, reused continuously during the projection; repetition of the preceding step with a shift of the impact point so that the impact points as a group cover the entire surface of the piece to be treated; a step for treatment by diffusion of chemical compounds into the nanostructured layer generated during the step for implementing the method for generating nanostructures.

Abstract: The present invention provides a nonvolatile memory card in which a program is added, modified, changed, or the like by selecting arbitrary firmware on a flash memory from a plurality of pieces of firmware on flash memories. In a memory card, in addition to a program stored in a built-in ROM, firmware on flash memories as programs for adding, changing, modifying, or the like of a function such as a patch program are stored. Firmware on a flash memory which is desired to be made valid is set in a parameter sector or the like and is loaded into an external RAM, and the CPU of a control logic executes a process.

Abstract: The present invention concerns a method for exchanging information between processes, tasks or computer applications executed by different operating systems coexisting on the same computer or the same hardware platform. This method allows communication between at least two client processes executed at the same time in a hardware platform (10) comprising one or more processors and storage means, at least part of which constitutes an addressable memory area that can be used as a working memory. These client processes are executed in two different operating systems (respectively) that are not directly compatible with one another. The method is characterized in that these the client processes write or read or modify information called exchange data in at least one common part, of the addressable memory of the hardware platform. The common part comprises an exchange memory.

Abstract: An IC card module includes first external connecting terminals and second external connecting terminals both exposed to one surface of a card substrate, a microcomputer connected to the first external connecting terminals, a memory controller connected to the second external connecting terminals, and a volatile memory connected to the memory controller. The shape of the card substrate and the layout of the first external connecting terminals are based on a standard of plug-in UICC of ETSI TS 102 221 V4.4.0 (2001-10). The second external connecting terminals are disposed outside the minimum range of the terminal layout based on the standard for the first external connecting terminals. The first and second external connecting terminals include signal terminals electrically separated from one another.

Abstract: Whether an initial command outputted from a host is ‘CMD1’ or ‘CMD55+CMD41’ is detected with an initial command detection portion 8, and the result of detection is set in an SD/MMC register 13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register 13. Thereafter, a microcomputer 7 sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register 14. A H/W-F/W mode comparison circuit 15 compares data in the SD/MMC register 13 with data in the F/W process SD/MMC register 14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer 7, and power-on reset processing is performed again.

Abstract: On an adapter mounting portion 3a having a projecting cross section which is formed on a cap 3 of a small-sized memory card 1, a recessed portion of an adapter 2 side is fitted so that both parts are formed as an integral unit in a replaceable manner. Accordingly, the small-sized memory card 1 can maintain the dimensional compatibility with respect to existing memory cards whereby the small-sized memory card 1 can be used also in equipment which is designed to cope with the existing memory cards.

Abstract: A blind rivet setting tool has a construction in which a tubular spring-biased handle gripped by an operator moves axially of the tool. An interlock between a trigger lever and the handle prevents operation of the tool until a rivet held by the tool is properly positioned in a hole of a workpiece.

Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.

Abstract: A multifunction IC card (MFC) has compatibility with a multimedia card, an SD card, etc. in that connector terminals (#1 through #13) are disposed on a card substrate (1) in two rows in a zigzag fashion, and realizes multifunction facilities in that a memory card unit (3) and an SIM (Subscriber Identity Module) card unit (4) are respectively exclusively connected and mounted to predetermined terminals of the connector terminals (#1 through #13). The memory card unit (3) and the SIM card unit (4) are respectively separately provided with areas for storing secrete codes for security. Thus, one IC card is capable of implementing multifunction facilities different in security level.