Patents Represented by Attorney, Agent or Law Firm Popham, Haik, Schnobrich & Kaufman, Ltd.
  • Patent number: 5538917
    Abstract: A fabrication method of a semiconductor integrated circuit device is provided. A patterned oxidation-resistant film such as silicon nitride film is formed on or over a semiconductor substrate. Using the patterned oxidation-resistant film as a mask, the substrate is then thermally oxidized so that a first oxide film for isolation is selectively formed to define active regions on the substrate. After the oxidation-resistant film is removed, the substrate is thermally oxidized so that a second oxide film is formed on the active regions, without adding any process step. Then, the substrate is etched until the second oxide film is entirely removed so that the surfaces of the active regions are exposed. During this process step, the first oxide film is partially removed. Subsequently, a patterned conductor film is formed on the first oxide film and then, it is removed from the first oxide.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: July 23, 1996
    Assignee: NEC Corporation
    Inventor: Masao Kunitou
  • Patent number: 5539221
    Abstract: An avalanche photodiode is provided which consists of a staircase APD with a periodic multilayer structure graded in composition from InAlAs to InGa.sub.x Al.sub.(1-x) As (x>0.1) as the multiplication layer to improve the dark current characteristic. Another photodiode with separate photoabsorption and multiplication regions is provided with an electric-field relaxation layer whose bandgap is wider than that of the photoabsorption and has a triple structure with a highly-doped layer sandwiched between lightly-doped layers. This photodiode incorporates in detail on an n-type InP substrate, an avalanche multiplication layer 13 of a periodic multilayer structure graded in composition from n.sup.- -InAlAs to InGa.sub.x Al.sub.(1-x) As, a p.sup.- -InGaAs photoabsorption layer 17, and an InP electric-field relaxation triple layer 16 consisting of n.sup.-, p.sup.+, and p.sup.- layers between the avalanche multiplication layer 13 and the photoabsorption layer 17.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: July 23, 1996
    Assignee: NEC Corporation
    Inventors: Masayoshi Tsuji, Kikuo Makita
  • Patent number: 5536358
    Abstract: The invention provides a method of estimating damage which a semiconductor substrate has suffered in a dry etching step included in a semiconductor fabricating step. The invention includes the steps of forming a delta-doped donor layer at a predetermined depth measuring from a surface of the semiconductor, measuring electron concentrations of the semiconductor before and after the dry etching step, and calculating a difference between the delta-doped donor concentrations to thereby quantitatively estimate a distribution of the damage throughout the depth of the semiconductor.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: July 16, 1996
    Assignee: NEC Corporation
    Inventors: Kazuaki Ashizuka, Hironobu Miyamoto
  • Patent number: 5535641
    Abstract: A rocker arm formed by pressing includes: a rocker arm body substantially U-shaped in section which is made of a plate material; and a roller rotatably supported between the side walls of the rocker arm body substantially at the middle, the rocker arm body having a semi-spherical pivot engaging portion at one end, and a valve engaging portion at the other end. In the rocker arm, each of the side walls has a pivot-side portion beside said pivot engaging portion which is smaller in wall thickness than the remaining.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: July 16, 1996
    Assignee: Koyo Seiko Co., Ltd.
    Inventors: Kazuo Uchida, Nobutsuna Motohashi
  • Patent number: 5535826
    Abstract: This invention relates to well-head structures, and particularly to so-called christmas trees, i.e. the complex of valves and pipes installed at a well-head to control the flow of high pressure oil or gas. The invention more particularly, but not exclusively relates to such structures for use in sub-sea structures. In order to accommodate all the required valves and pipes, known trees are normally undesirably high--i.e. of the order of 18 feet or so. In order that trawler nets do not snag on such trees, expensive protection structures or well reinforcing may be required to be installed around each tree. However, the present invention provides a christmas tree including a valve assembly comprising one or more valves installed at a well-head to control the flow of produce thereat, at least one of the one or more valves being retained within an outlet of the well-head.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: July 16, 1996
    Assignee: Petroleum Engineering Services Limited
    Inventors: Stuart C. Brown, James Crabb
  • Patent number: 5536936
    Abstract: This invention concerns a spectroscopic ellipsometer modulated at a frequency (.omega..sub.m) intended for taking measurements of a sample (3). The spectroscopic ellipsometer is phase modulated, the sample being excited by external means (16) producing periodic, alternating excitation at a frequency (.OMEGA..sub.e). The measurement contains the ellipsometric parameter values (.psi., .DELTA.) of the sample, respectively in the presence of (.psi..sub.1, .DELTA..sub.1) and in the absence of (.psi..sub.2, .DELTA..sub.2) excitation of the sample, as a function of excitation frequency (.OMEGA..sub.e).
    Type: Grant
    Filed: January 11, 1995
    Date of Patent: July 16, 1996
    Assignee: Centre National de la Recherche
    Inventors: Bernard Drevillon, Jean-Yves Parey, Razvigor Ossikovski
  • Patent number: 5535823
    Abstract: Apparatus (50) for amplifying a load applied by a wireline to a tool in a borehold includes a housing (4). A first coupling device (51) couples the wireline to the apparatus (50) and a second coupling device (60) couples the tool to the apparatus (50). The second coupling device (19) is movably mounted within the housing (4) and the transmission mechanism (9, 14,16) interconnects the first and second coupling devices. The transmission mechanism permits a mechanical advantage and comprises a first linearly movable member (9) coupled to the first coupling device (51) and a second linearly movable member (16) coupled to the second coupling device (19). The first and second members (9, 16) are interconnected by a rotatable member (14) such that movement of the first member (9) rotates the rotatable member (14) to move the second member (16). The movement of the second member (16) is less than the movement of the first member (9) and so the apparatus (50) generates a mechanical advantage.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: July 16, 1996
    Assignee: Well-Equip Limited
    Inventor: Michael A. Reid
  • Patent number: 5535988
    Abstract: If the load applied on the load sheave is small, the pressing drive member contacts tightly with the friction members to make secure the braking of rotation of the drive shaft, so that the small load is prevented from moving downward by its own gravity, and moreover the operation wheel is engaged with and held in the rotation limiting member spline-coupled with the drive shaft so as to be free to idle even in a no-load state, and a spring for pressing the operation wheel to the rotation limiting member is inserted between the outer end surface of the operation wheel and the spring retainer held on the drive shaft projecting from the rotation limiting member.
    Type: Grant
    Filed: January 27, 1994
    Date of Patent: July 16, 1996
    Assignee: Vital Kogyo Kabushiki Kaisha
    Inventor: Yosaku Nishimura
  • Patent number: 5534086
    Abstract: A dispersion-strengthened copper alloy is disclosed having an exceptional combination of strength, ductility, and thermal conductivity. The copper alloy comprises: copper, 0.01 to 2.0 weight % boron and 0.1 to 6.0 weight % cobalt, and cobalt-boride disperoids that range in size between 0.025 and 0.25 microns in diameter. A copper alloy is made by rapid solidification of the melt into a powder. Strong, thermally conductive articles can be made by compacting the powder at temperatures below the melting temperature of the copper alloy, and optionally warm working, cold working, and annealing.
    Type: Grant
    Filed: May 1, 1995
    Date of Patent: July 9, 1996
    Assignee: United Technologies Corporation
    Inventor: James S. Andrus
  • Patent number: 5534085
    Abstract: A method of treating low-expansion Fe--Ni--Co superalloys is disclosed in which the alloys are forged at a temperature below the recrystallization temperature and then recrystallized without the use of intervening annealing steps. It is necessary that the warm forging step introduce sufficient strain throughout the Fe--Ni--Co superalloy such that after recrystallizing, the superalloy has a substantially uniform microstructure. Alloys produced by this method exhibit good hydrogen charging embrittlement resistance, good strength and/or rupture ductility in moist air.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: July 9, 1996
    Assignee: United Technologies Corporation
    Inventors: Fred P. Cone, Stephen V. Prece, Donn A. Best
  • Patent number: 5535163
    Abstract: A multibit semiconductor memory device for inputting and outputting data in a parallel fashion in a unit of bits. The multibit memory has a memory cell array composed of mixed memory cells corresponding to different IO bits, data I/O terminals corresponding respectively to IO bits, an address terminal for inputting an address and internal data buses associated respectively with the IO bits and connected to the memory cell array. Further, the memory device has a test mode entry signal generator for generating a test mode entry signal indicative of entry into a test mode, a pseudo-address generator connected to the address terminal, for generating a pseudo-address in the test mode, and a connecting circuit responsive to the test mode entry signal for selecting one of the internal data buses depending on the pseudo-address and connecting the selected bus to predetermined one of the data I/O terminals.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: July 9, 1996
    Assignee: NEC Corporation
    Inventor: Yoshinori Matsui
  • Patent number: 5532610
    Abstract: The apparatus for collectively burning-in or testing a plurality of semiconductor chips disposed on a wafer without dicing the chips into individuals, the apparatus including a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on the wafer to be tested, a plurality of pads disposed on the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer, and an anisotropic conductive layer disposed on the pads.
    Type: Grant
    Filed: August 25, 1994
    Date of Patent: July 2, 1996
    Assignee: NEC Corporation
    Inventors: Tohru Tsujide, Toshiyasu Hishii, Kazuo Nakaizumi
  • Patent number: 5529947
    Abstract: On a first surface of a first single crystal silicon substrate, in which a silicon dioxide layer having gradually tapered peripheral edge (tapered wall), a second single crystal silicon substrate is clad. On the second surface of the first single crystal silicon substrate, an island form polycrystalline silicon region is isolated from remaining region by an isolation groove to form an element. By reducing step between the buried silicon dioxide layer and the first single crystal silicon substrate, local concentration of a stress can be successfully avoided. Also, abrasion of the silicon oxide layer and single crystal silicon substrate having mutually different etching speeds is not performed so that the step can be lowered to eliminate formation of void. Between the first surface of the first single crystal silicon substrate formed with the elements and the cladding surface, the silicon dioxide layer is present to avoid influence of contaminant penetrating during cladding process.
    Type: Grant
    Filed: December 15, 1994
    Date of Patent: June 25, 1996
    Assignee: NEC Corporation
    Inventor: Kensuke Okonogi
  • Patent number: 5530620
    Abstract: A system and method for upgrading a computer is disclosed. Certain essential chips present in the original computer system are functionally, but not necessarily physically, removed from the computer system. Functions which would otherwise be performed by the original chips are instead performed by higher-performance chips on a plug-in module which is plugged into the computer system. The functional removal of the certain chips from the original computer system is achieved through simple insertion of the plug-in module. No replacement or substitution of original chips or boards is necessary. Furthermore, upgraded computer systems may be further upgraded by replacement of a first plug-in module with a second plug-in module with different performance characteristics. The upgrade capability is accessible from outside the cabinet, to avoid opening the cabinet to upgrade the system. Advantageously, means are provided for ensuring that the module cannot be inserted or removed when system power is turned on.
    Type: Grant
    Filed: June 18, 1993
    Date of Patent: June 25, 1996
    Assignee: Advanced Logic Research, Inc.
    Inventor: Vic Sangveraphunsiri
  • Patent number: 5530306
    Abstract: In a magnetic bearing apparatus, a rotating member having an axis of rotation along the horizontal direction is supported by a pair of radial magnetic bearings each including a plurality of electromagnets in the radial direction with clearances with the rotating member in two portions in the axial direction. The apparatus comprises a pair of position detecting sensors for detecting the displacement in the radial direction of the rotating member in the two positions in the axial direction of the rotating member and a control device for controlling magnetic attraction forces produced by the electromagnets on the basis of output signals from the respective sensors.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: June 25, 1996
    Assignee: Koyo Seiko Co., Ltd.
    Inventor: Hirochika Ueyama
  • Patent number: 5528947
    Abstract: A rod pumping unit used in the oil field, which has high efficiency and saves power, characterized in that: for the connection of the 2.omega. crank and the main crank in the 2.omega. crank balance device there is provided a differential phase adjusting mechanism, for the walking beam balance there is provided beam balance mass lowering device having positioning mechanism or self positioning mechansim, these devices can be adjusted manually in non-stopped status or by computer. The advantages of the pumping unit of the present invention are that the torque fluctuation of the speed reducer is small, the negative work of the power machine is eliminated and the power consumption and the total weight of the machine are decreased greatly. The present invention may save power and material to 50% as compared with the conventional beam pumping unit.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: June 25, 1996
    Inventors: Pucheng Wang, Jia Wang, Qi Wang
  • Patent number: 5529958
    Abstract: The present invention relates to a method of manufacturing a semiconductor device, including the steps of forming, on a silicon substrate, a metal film to be converted into a silicide, continuously forming a thin film on the metal film, and performing annealing of a structure body constituted by the silicon substrate, the metal film, and the thin film at a temperature at which the metal film is reacted with the silicon substrate.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: June 25, 1996
    Assignee: NEC Corporation
    Inventor: Akihiro Yaoita
  • Patent number: 5530294
    Abstract: A contact of a semiconductor device has an interlayer-insulating film sandwiched between upper and lower conductive line patterns, a conductive pad for electrically connecting the upper and lower conductive line patterns via a contact hole formed in the interlayer-insulating film to expose the lower conductive line pattern to the upper conductive line pattern, and a barrier material pattern formed on the upper conductive line pattern and conductive pad to partially overlap the conductive pad with the upper conductive line pattern, so that the lower and upper conductive line patterns on both sides of the interlayer-insulating film partially overlap with each other without damaging the lower conductive line pattern, thereby improving packing density of the semiconductor device. Also, a manufacturing method of the contact is provided.
    Type: Grant
    Filed: April 14, 1995
    Date of Patent: June 25, 1996
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jae K. Kim
  • Patent number: 5525840
    Abstract: A semiconductor device has an alignment mark formed as a diffraction grating which comprises a plurality of unit markers arranged so that the period P of the diffraction grating is 8 .mu.m. The length d.sub.1 of each unit marker in the scanning direction of a laser beam is 4 .mu.m while the length L thereof in a direction perpendicular to the scanning direction is 4 .mu.m. Each unit marker comprises nine unit segments each of 0.8 .mu.m.times.0.8 .mu.m in size and arranged in an array of 3.times.3. Submicron openings constituting an unit segment has a small size for sufficiently filling the openings with deposited metal. An accurate alignment can be obtained by the alignment mark in an optical stepper for manufacturing semiconductor devices.
    Type: Grant
    Filed: November 9, 1994
    Date of Patent: June 11, 1996
    Assignee: NEC Corporation
    Inventor: Makoto Tominaga
  • Patent number: D371888
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: July 16, 1996
    Assignee: Phillip E. Tingler
    Inventor: Eugene A. Tingler