Patents Represented by Attorney Rabin & Berdo, P.C.

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  • Charge-pump phase-locked loop circuit with charge calibration
    Patent number: 6608511
    Abstract: A charge-pump phase-locked loop (PLL) circuit with charge calibration. The PLL keeps the phase of an output clock signal constant in a “locked” condition, and includes a first charge pump, a second charge pump and a charge sensing circuit. The first and the second charge pumps provide a first current and a second current, respectively. According to a first and second net charge delivered from the first and the second currents separately, the charge sensing circuit provides a calibrate voltage signal as feedback to the first charge pump and the second charge pump. Under control of the calibrate voltage signal, the first and the second charge pumps regulate the first net charge and the second net charge to become exactly zero thereby maintaining the phase of the output clock signal locked onto the phase of a reference clock signal.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: August 19, 2003
    Assignee: Via Technologies, Inc.
    Inventor: Wei-Chan Hsu
  • Analog signal input circuit in analog signal processing apparatus
    Patent number: 6608583
    Abstract: An analog signal input circuit having sample-hold circuit that is constituted by a switched capacitor amplifier for which the gain is controlled according to the capacitance ratio of the plurality of capacitors connected with a switch group, for which the opening and closing is controlled according to the amplification rate setting command. The clamping voltage of a clamping circuit included in the analog signal input circuit is established in compliance with an amplification rate setting command.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: August 19, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takashi Konno
  • Semiconductor device and production process thereof
    Patent number: 6605490
    Abstract: A semiconductor device having a pad for electrical connection provided on a semiconductor substrate, a first insulating film with which a surface of the semiconductor substrate is coated and having an opening to which the pad is exposed, a conductive film joined to the pad on a bottom surface of the opening of the first insulating film and extending to a surface of the first insulating film outside the opening, a second insulating film with which the conductive film is coated and having an opening to which a part of the conductive film is exposed, and a connecting member arranged so as to be joined to the conductive film inside the opening of the second insulating film.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: August 12, 2003
    Assignee: Rohm Co., Ltd.
    Inventor: Kazutaka Shibata
  • Long seek control system and method in an optical storage device
    Patent number: 6606282
    Abstract: The long seek control system and method include a reference velocity mapping unit that obtains a reference velocity when the dual actuator is moved by the residual track count; a velocity estimator for outputting an estimated velocity and obtaining a sled control effort by subtracting the estimated velocity from the reference velocity; and an electrical damper for receiving the sled control effort and simultaneously receiving the displacement of the dual actuator to output a damping control effort to the fine actuator, and reduce the vibration of the fine actuator during the long seek operation. In the reference velocity mapping unit, a reference velocity curve is used to describe the mapping relation between the residual track count and the reference velocity. The reference velocity curve includes a linear part and several quadratic parts with different quadratic functions.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: August 12, 2003
    Assignee: Acer Laboratories Inc.
    Inventors: Wei-Chou Hung, Chih Long Dai
  • Automatic transaction system
    Patent number: 6604680
    Abstract: An automatic transaction system is provided which is capable of easily transmitting money between a payer or a recipient even if the recipient has no account in a financial institution. The automatic transaction system includes an automatic teller machine (ATM), a terminal, and a connecting device. The automatic transaction system is made up of a storing section, an obtaining section, and a communicating unit. The connecting device has a destination designating section. The terminal has a recognizing unit, an inputting section, and a communicating section.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 12, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshitaka Hamaguchi
  • Surface mount type semiconductor package and manufacturing method therefor
    Patent number: 6605867
    Abstract: A conductive layer is formed on a dielectric substrate on which a semiconductor chip is mounted, and holes are formed passing through the layer and the substrate. After this, before the through-holes are filled with a conductive material, the conductive layer is patterned by patterning. By patterning, conductive patterns are formed from the conductive layer. After the conductive patterns are formed, the through-holes are filled with a conductive material while both ends of the holes are open, to form conductors. In the above process, one open end of each through-hole is used as a leak hole to discharge air bubbles, thus suppressing the occurrence of voids caused by bubbles, and an increase in electrical resistance in the conductors by voids can be prevented.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 12, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Shigeru Yamada
  • Method of manufacturing alignment mark
    Patent number: 6601314
    Abstract: A method for manufacturing a highly reliable alignment mark in which by-products do not form at an aligning mark position during patterning. In this method, an intermediate layer is disposed on an upper layer of a first wiring to protect the first wiring. Then, a filling material is coated thereon to fill in a through hole. Thereafter, a plug is formed by etch-backing, and a second wiring is formed.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: August 5, 2003
    Assignee: Oki Electric Industry Co, Ltd.
    Inventors: Satoshi Machida, Akiyuki Minami
  • Carrier reel, carriage method using the carrier reel, and method for manufacturing electronic device
    Patent number: 6602305
    Abstract: A carrier reel according to the present invention is constituted by a flange portion having a first surface and a second surface which is opposed to and substantially parallel to the first surface, and a hub portion which is provided between the first surface and the second surface and to which the flange portion is connected. A bearing portion at which a shaft used for taking out each electronic component after carriage is supported is provide to the hub portion, and spaces for accommodating therein a drying agent, i.e., drying agent accommodating portions are formed at the part of the hub portion except the bearing portion. The drying agent is accommodated in the drying agent accommodating portions. The carrier reel having the drying agent accommodated therein is put in a damp proof bag to be sealed. The sealed damp proof bag is then packaged to be carried.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: August 5, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Seiichi Kawada
  • Transceiver circuit transmitting/receiving a tenary pulse signal
    Patent number: 6603805
    Abstract: A half-matching type transceiver circuit which only requires a reduced area for mounting. A coupling transformer has a primary winding with one end and the other end connected to balanced transmission lines, and a secondary winding with one end and the other end connected to output terminals of first and second tristate buffers, respectively. These tristate buffers are supplied at their respective input terminals with a high potential driving pulse signal corresponding to information data at shifted timings to generate a ternary transmission pulse signal on the balanced transmission lines.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: August 5, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Ryuji Hisano, Hiroyuki Kanbara
  • Chipset with clock signal converting
    Patent number: 6603828
    Abstract: A signal converting device and method for converting signals from memory interfaces into main system interfaces. The present invention can completely convert response signals from high frequency devices into low frequency devices, for solving low efficient and disadvantages caused by asynchronous conversion. The signal loss is not occurred when the signal converting device is in pseudo synchronization. By applying the present invention, the computer system can work normally and rapidly, in which the frequency of the request signals from the main system interface is higher than half of the frequency of the response signals from the memory interface. The compurter system is, for example computer system for 100 MHz/133 MHz or 66 MHz/100 MHz.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: August 5, 2003
    Assignee: Via Technologies, Inc.
    Inventor: You-Ming Chiu
  • Phase-detecting device
    Patent number: 6603300
    Abstract: A phase detecting device, including a phase detector, an inversion logic circuit, a latch and an OR logic circuit, is used for detecting the phase difference between a reference signal and a feedback signal and for outputting a delay control signal. The phase detector generates a detected signal according to the status of the feedback signal captured by the reference signal. The inversion logic circuit inverts the detected signal, and the delay device delays the detected signal. The delayed inverted detected signal is then fed into the latch device to generate a latch signal. As the detected signal and the latch signal are fed into the OR logic circuit, the OR logic circuit feeds the delay control signal into the counter so that the delay circuit can generate different delay time, such as T/4, T/2 or 1T, for meeting different signal-delay requirements.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: August 5, 2003
    Assignee: Via Technologies, Inc.
    Inventors: Yu-Wei Lin, Chia-Hsin Chen
  • Electric power steering system
    Patent number: 6600280
    Abstract: An electric power steering system is provided which employs an electric motor as a driving source to apply a steering assist force to a steering mechanism. The system includes: an operation degree detecting section for detecting an operation degree of an operation member; a motor current detecting section for detecting an electric current flowing through the electric motor; and a steering angle detecting section for detecting a steering angle of the steering mechanism. A reaction force from a road surface is computed on the basis of outputs of the operation degree detecting section, the motor current detecting section and the steering angle detecting section, and a driving target value of the electric motor is determined on the basis of the reaction force and the operation degree of the operation member.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: July 29, 2003
    Assignee: Koyo Seiko Co, Ltd.
    Inventor: Koji Kanda
  • Externally mounted speaker for notebook computer
    Patent number: 6600827
    Abstract: An externally mounted speaker for a notebook computer mainly has a moveable speaker box assembled on the back side of a screen; when the screen is in a vertical position, the speaker box can be pulled out of a box mounting slot to protrude outward and face directly across the user for obtaining the most stereo sound effect.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: July 29, 2003
    Inventor: Liang-Chi Lu
  • Semiconductor device
    Patent number: 6600361
    Abstract: A semiconductor device comprises a first current mirror circuit (101) which has an input terminal (101I) and an output terminal (101O), a second current mirror circuit (102) which has an input terminal (102I) and an output terminal (102O) wherein the input terminal (102I) is coupled with the output terminal (101O) wherein the output terminal (102O) is coupled with said input terminal (101I) and a start-up circuit (103) which supplies current to input terminal (102I) based on voltage on the input terminal (101I).
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: July 29, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masafumi Nagaya, Masahiko Nakajikkoku
  • Method and apparatus for displaying test results and recording medium
    Patent number: 6601201
    Abstract: There are provided a method and an apparatus for displaying test results and a recording medium, which allow easy detection of Devices for Testing in which probes are destroyed. The apparatus has two wafer probers, a work station, and a PC. On the basis of a display program and a display mode switching program stored in a ROM of the work station, respective test results of testing semiconductor chips by the two wafer probers are displayed on a CRT of the PC in correspondence to positions of the semiconductor chips on a wafer substrate, and, at the same time, a pass/ fail ratio for each of the DFT's is displayed in parallel with the test results of the semiconductor chips.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: July 29, 2003
    Assignee: Oki Electric Industry Co, Ltd,
    Inventor: Toshiaki Kato
  • Corkscrew
    Patent number: D477973
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: August 5, 2003
    Assignee: Ko Fung Products Industrial Limited
    Inventor: Kwok Leung Yu
  • Mobile phone holder
    Patent number: D478074
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: August 5, 2003
    Assignee: Sky City International Limited
    Inventor: Man Kuen Lam
  • Cheese grater
    Patent number: D478254
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: August 12, 2003
    Inventor: Mei Ying Chau
  • Hand electric control device
    Patent number: D478330
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: August 12, 2003
    Inventor: Tai-Her Yang
  • Electrostatic discharge protection circuit triggered by capacitive-coupling
    Patent number: RE38222
    Abstract: An electrostatic discharge (ESD) protection circuit connected to an integrated circuit pad for protecting an internal circuit from ESD damage. The ESD protection circuit includes an NMOS/PMOS transistor, a capacitor, and a load The NMOS/PMOS is configured with a drain connected to the IC pad and a source for connection to the circuit VSS/VDD. Agate of the NMOS/PMOS transistor is tied to the source. The capacitor is connected between the IC pad and the bulk of the NMOS/PMOS transistor The load, which is either another NMOS/PMOS transistor or a resistor, is to be connected between the VSS/VDD and the bulk of the NMOS/PMOS transistor. In accordance with the invention, the NMOS/PMOS transistor is fabricated in a P-well/N-well region of a semiconductor substrate. The capacitor includes an IC pad and a polysilicon layer therebelow, with an intervening dielectric layer.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: August 19, 2003
    Assignee: Winbond Electronics Corp.
    Inventor: Chau-Neng Wu