Abstract: A method and apparatus for forming silicon spheres (40) from irregular-shaped particles (38) for use in solar cells are disclosed. The apparatus (10) generally comprises a vertically aligned cylindrical chamber (12) having an abrasive lining (32) integrally formed therein. The abrasive lining (32) is preferably a silicon carbide material. A gas source (36) is tangentially injected into the chamber (12) to create an gas vortex inside the chamber (12). This vortex induces the repeated collision of the particles (38) against the abrasive lining (32) to eventually form the silicon spheres (40) and simultaneously sizing the silicon spheres (40).

Abstract: A complementary semiconductor structure comprises a substrate of a first conductivity type upon which a first channel layer of a second conductivity type is formed. The first source/drain layer of the first conductivity type is formed on the surface of the first channel layer and an insulating layer is formed on the surface of the first source/drain layer. A second source/drain layer of the second conductivity type is formed on the surface of the insulating layer and a second channel layer of said first conductivity is formed on the surface of the second source/drain layer. A third source/drain layer of the second conductivity type is formed on the surface of the second channel layer. Gate circuitry is vertically disposed on an edge perpendicular to the plane and adjacent to the first and second channel layers and insulated therefrom.

Abstract: A process for making CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat. A titanium nitride layer may be formed by depositing titanium metal everywhere, and then heating the integrated circuit structure in a nitrogen atmosphere. This process may also be used with other refractory metal nitride interconnect layers. In addition to titanium based thin film compositions, other metals can be substituted and used for direct-react silicidation and simultaneous formation of a conductive nitride to form local interconnects, including molybdenum, tungsten, vanadium, cobalt, and others.

Abstract: The disclosure relates to a radiation heat shield which is formed of graphite which covers the open end of the crucible of a furnace for forming single crystals of silicon by the Czochralski method. The graphite preferably has a silicon carbide coating thereon. The heat shield is preferably formed in plural segments with a counterweight at one end of each of the segments whereby, upon raising of the crucible, the segments and associated counterweight rotate about a pivot to expose the top of the crucible.

Abstract: A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

Abstract: A digital signal processor includes a parallel multiplier having first and second input ports, in which the first input port has conductors for many more bits than does the second input port. First and second data selectors are connected respectively to the first and second ports to enable data from a RAM and data from a ROM to be selectively applied to either or both ports, directly or via a pipe-line register. The second data selector can select two or more groups of bits from the RAM or ROM to enable the multiplier to multiply numbers having more bits than can be input at the second input port at one time. A third data selector is connected to the output port of the multiplier and is capable of shifting the product received relative to the output conductors to effect multiplication by powers of two. A particular application of the processor is for processing pulse coded speech signals.

Abstract: An end effector (10) is pivotally affixed to a robot arm (12) and comprises a platform (28) and a catcher (42). In operation, the end effector (10) picks up an integrated circuit slice (S), tilts the platform (28) away from the horizontal, causing the slice (S) to slide into an indexing surface (47) of the catcher (42). This places the slice (S) in a predetermined position relative to the robot arm (12) allowing for precise placement of the slice (S) at a workstation (106).

Abstract: A voltage overstress protection device consists of a four-layer diode having a buried region of higher impurity concentration adjacent the central junction of the device. The buried region is divided into a plurality of small regions to ensure an even distribution of energy dissipation across the structure. The cathode of the device may be perforated by shorting dots of the material of the second layer to determine the holding current of the device, and where this is done the small buried regions are aligned with parts of the cathode and not with the shorting dots. Two devices may be formed in opposite senses in the same body of semiconductor material and connected together in antiparallel to provide protection against voltage surges of either polarity. Two antiparallel pairs of devices may be formed in a single semiconductor body to provide protection against separate voltage surges on two lines and also against different voltage surges between the two lines.

Abstract: Semiconductor memory device including a dynamic memory array having a plurality of dynamic memory cells arranged in a matrix of rows and columns, write line and read line buffer memories disposed at the input and output of the dynamic memory array, and internal control circuitry including an internal refresh circuit and an internal arbiter circuit for determining relative priority as between write, read, and refresh request signals such that the internal refresh circuit is enabled to generate a refresh request signal for periodically applying a refresh signal to the dynamaic memory cells of the dynamic memory array without requiring an external control signal for implementation of the refresh request signal.

Abstract: A method for forming CVD tungsten contacts in a planarized semiconductor body. The method utilizes aluminum as an etch mask and etch stop to prevent etching of underlying layers during contact formation.

Abstract: A method for etching a tungsten film which includes introducing activated species of a halogenated hydrocarbon to the tungsten film.

Abstract: A digital data storage circuit for a digital signal processor which is capable of receiving asynchronous inputs and is such as to be testable by selectively configuring the storage circuits as a shift register enabling the entry and extraction of test data in the processor. The storage circuit includes two latch elements each formed by two complementary transistor inverter circuits connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it. Asynchronous inputs are applied to a first latch element through switch means comprising a complementary transistor inverter responsive to a SET input in series with a transistor responsive to a CLEAR input. The complementary inverter is connected to the input of the first latch element through a series connected transistor.

Abstract: An apparatus and a method for the etching of semiconductor materials is disclosed. The apparatus includes a process chamber which includes a plasma generator remote from and in fluid communication with the process chamber. The remote plasma generator includes an inlet tube, a discharge tube in fluid communication with the inlet tube, an excitation cavity surrounding the discharge tube, an outlet tube in fluid communication with the discharge tube and a process chamber, and an injection tube in the outlet tube.

Abstract: A cost-effective word recognizer. Each frame of spoken input is compared to a set of reference frames. The comparison is equivalent to embodying the reference frame as an LPC inverse filter, and is preferably done in the autocorrelation domain. To avoid the instability and computational difficulties which can be caused by a high-gain LPC inverse filter, a noise floor is introduced into each reference frame sample. Thus, for each input speech frame, a scalar measures its similarity to each of the vocabulary of reference frames.To achieve connected word recognition based on this similarity measurement, a dynamic programming algorithm is used in which time warping to match a sample to a reference is in effect permitted, and in which matching is performed with unconstrained endpoints.

Abstract: A driver circuit for switching on lamps with low cold resistance. The circuit includes a power transistor (T5) of which the collector-emitter path is connected to the lamp (12) in a series circuit which lies between a positive terminal and a ground terminal of a supply voltage source. The circuit further includes an RC member comprising a resistor (R1) which is connected on one side to the ground terminal and a capacitor (C) which is connected in series with the resistor and on one side to the positive terminal of the supply voltage source. A comparator (38) compares the voltage at the resistor (R1) with the voltage at the collector of the power transistor (T5) and furnishes at an output a blocking signal for the power transistor (T5) when the voltage at the resistor (R1) is more negative than the voltage at the collector. A limiting member (T4) limits the voltage at the resistor (R1) to a voltage value lying above the saturation voltage of the power transistor (T5).

Abstract: A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.

Abstract: A plasma dry etch process for etching deep trenches in single crystal silicon material with controlled wall profile, for trench capacitors or trench isolation structures. HCl is used as an etchant under RIE conditions with a SiO.sub.2 hard mask. The SiO.sub.2 hard mask is forward sputtered during the course of the Si etch so as to slowly deposit SiO.sub.x (x<2) on the sidewalls of the silicon trench. Since the sidewall deposit shadows etching at the bottom of the trench near the sidewall, the effect of this gradual buildup is to produce a positively sloped trench sidewall without "grooving" the bottom of the trench, and without linewidth loss. This process avoids the prior art problems of mask undercut, which generates voids during subsequent refill processing, and grooving at the bottom of the trench, which is exceedingly deleterious to thin capacitor dielectric integrity.

Abstract: A semiconductor device package assembly including a semiconductor chip (10) which contains an electronic circuit and is mounted on a support plate (12) of electrically conductive material. Disposed substantially in the plane of the support plate (12) are conductor strips (18) which extend in the direction towards the support plate (12) and at their ends remote from the support plate (12) are formed as terminal conductors (22) for establishing connections to external electronic circuits. Selected conductor strips (18) are connected to selected points of the electronic circuit in the chip (10). A housing is provided which encloses the support plate (12), the semiconductor chip (10) and the conductor strips (18) and out of which the terminal conductors (22) project. At least one of said terminal conductors (22) serves for the application of ground.

Abstract: Electron beam apparatus for use in testing integrated circuits uses a magnetic electron objective lens having a first end adjacent the circuit under test and a second end remote from the circuit. The magnetic field of the lens increases steeply to a maximum near the first end and falls gradually towards the second end. Secondary electrons emitted from the circuit are accelerated strongly by an electrostatic field into the first end of the lens and are retarded abruptly to speeds of the same order as their emission speeds in the region of maximum magnetic field. Further gradual retardation of the electrons takes place so that the electrons approach the second end of the lens parallel to the axis of the lens at substantially their emission speeds. A filter grid located at the second end of the lens and a collector of electrons passing through the filter grid enable the emission speeds of the secondary electrons to be measured.

Abstract: A sense amplifier 10 for a memory or logic array has a bipolar device transistor 11 that is kept from saturating by one or more unipolar transistors (12, 13) coupled between the collector (18) and base (17) of the bipolar transistor 11.