Abstract: A labeling system combines an indelibly inscribed visually readable serial number with an embedded electronically readable one-time programmable read-only storage device. The integration of the two in one labeling system ensures that the visually readable identification information is consistent with the electronically readable information. The labeling system is tamper evident visually and electronically. Electronic tamper evidence is provided by the construction of the label system which is designed to ensure the breaking of various internal and peripheral electrical connections associated with the embedded read-only storage device during any attempt to remove the label once it is affixed to the computer or subassembly thus identified. The integration of visual and electronic identification information eliminates the need to manually or electronically enter the identification information into the electronic storage device during a separate manufacturing process.

Abstract: A method and system for marking and subsequently retrieving a collection of objects contained within a compound document. The compound document is displayed within a graphical user interface within a data processing system. The graphical user interface includes a scroll bar. A collection of objects within a portion of the compound document may be selected by a user. Thereafter, a horizontal line is displayed within the scroll bar which corresponds to the relative location of the collection of objects within the compound document. Next, in response to a user input, a dialog box is displayed at a location adjacent the horizontal line. The graphical user interface next prompts a user to enter within the dialog box a label and attributes of the collection of objects.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of the value that was most recently read, and that cache is marked as containing the most recently read copy, while the remaining caches are marked as containing shared, unmodified copies of the value. When a requesting processing unit issues a message indicating that it desires to read the value, the specific cache transmits a response indicating that it cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit.

Abstract: A method and system for automatically performing one or more operations on multiple computer systems within a cluster are disclosed. In accordance with the present invention, a begin operations command construct is defined within an input file. In addition, an input command indicating one or more operations to be performed on at least two computer systems within the cluster and an end operations command construct are defined. In response to a selected input, one or more operations indicated by the input command are automatically performed on at least two computer systems. In accordance with one embodiment, the begin operations command construct indicates selected computer systems within the cluster on which the one or more operations are to be performed and whether the operations are to be performed on the selected computer systems serially or in parallel.

Abstract: A method of accessing a cache used by a processor of a computer system, to eliminate arbitration logic which would otherwise be required to handle operations from multiple snooping devices. A plurality of cache directories are provided in the cache, respectively connected directly to a plurality of snooping devices using a plurality of interconnects. An operation from a given snooping device is then handled by using a respective cache directory to issue a response to a respective interconnect. For example, a first cache directory may be connected to a first interconnect on a processor side of the cache, and a second cache directory may be connected to a second interconnect on a system bus side of the cache. This construction allows handling of operations from multiple snooping devices without having to use critical path arbitration logic. Furthermore, this construction allows for improved cache access due to the physical placement of the multiple cache directories.

Abstract: A method of delivering data in an on-time manner across a communicating environment, such as multimedia data in a network or broadcast environment. The data is transmitted from a data pump at a revised transmission time which is a function of a base transmission time and a delay value. The delay value is calibrated by monitoring one or more processes between the data pump and an associated controller which receives requests from clients. The controller may include an application server which handles the requests, and a control server which processes commands from the application server and provides corresponding control functions to the data pump.

Abstract: A method and system of providing a cache-coherency protocol for maintaining cache coherency within a multi-processor data-processing system is disclosed. In accordance with the method and system of the present invention, each processor has a cache hierarchy of at least a first-level cache and a second-level cache, and the first-level cache is upstream of the second-level cache. Each of the caches includes multiple cache lines, each associated to a state-bit field utilized for identifying at least six different states of the cache lines, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state. In response to an indication of a cache line containing a copy of information that was most recently accessed, the state of the cache line is transitioned from the Invalid state to the Recently-Read state.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from an address of a memory device of the computer system, and each cache snoops the interconnect to detect the message.

Abstract: A method and system for front-end gathering of store instructions within a processor is disclosed. In accordance with the method and system of the present invention, a store queue within a data-processing system includes a front-end queue and a back-end queue. Multiple entries are provided in the back-end queue, and each entry includes an address field, a byte-count field, and a data field. A determination is first made as to whether or not a data field of a first entry of the front-end queue is filled completely. In response to a determination that the data field of the first entry of the front-end queue is not filled completely, another determination is made as to whether or not an address for a store instruction in a subsequent second entry is equal to an address for the store instruction in the first entry plus a byte count in the first entry.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into at least two caches, the caches are marked as containing shared, unmodified copies of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, a given one of the caches transmits a response indicating that the given cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit.

Abstract: A method and system for transferring data between buses having different ordering policies via the use of autonomous units capable of being replicated and layered. The autonomous units include a plurality of execution units which are grouped and assigned a class of data operations for each group. Within each group the operations are ordered according to the sequence in which they were received without regards to outstanding operations in other groups. An intra unit is responsible for prioritizing the ordered operations for all groups in accordance with the a selected one of the ordering policies.

Abstract: A method of reducing memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. When a requesting processing unit issues a message indicating that it desires to read a value from an address of a memory device of the computer system, each cache snoops an interconnect to detect the message, and transmits a response to the message, wherein a shared intervention response is transmitted to indicate that a cache containing an unmodified value corresponding to the address of the memory device can source the value. A priority is associated with each response, and system logic detects each response and its associated priority, and forwards a response with a highest priority to the requesting processing unit. The protocol may include prior-art coherency responses such as an invalid response, a modified intervention response, a shared response, and a retry response. Either the retry response or the shared intervention response may be assigned a highest priority.

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

Abstract: A data processing system and method of communicating data are provided. The data processing system includes a communication network to which a number of devices are coupled. According to the method, a timing signal having a selectable frequency is generated. Data is then communicated across the communication network between two of the devices in response to the selectable frequency of the timing signal. Thus, data is communicated at a first rate in response to the selectable frequency being set to a first frequency and is communicated at a second rate in response to the selectable frequency being set to a second frequency. In one embodiment, at least one of the devices includes communication control logic that can be selectively operated at the fixed-frequency of a clock signal.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is assigned a current priority, at least the highest current priority being determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

Abstract: A method and apparatus in a data processing system for selecting a particular object from among a large number of objects utilizing a selector icon displayed within the data processing system. In response to user input, an extended region of the selector icon is displayed. The extended region includes scan speed indicia such as a lined scale. A selection indicium is moved into the extended region, and thereafter, a particular scan speed indicium from among a large number of scan speed indicia is selected. Thereafter, a particular object is scanned from among a large number of objects at a scanning speed related to the selected scan speed indicia such that a particular object from among a large number of objects may be efficiently located. Objects chosen may be numbers from among a large group of numbers.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requesters that share the resource. Each of the requesters is associated with a priority weight that indicates a probability that the associated requester will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requesters. In response to the current priorities of the requesters, a request for access to the resource is granted. In one embodiment, a requester corresponding to a granted request is signaled that its request has been granted, and a requester corresponding to a rejected request is signaled that its request was not granted.

Abstract: A method, memory, and apparatus directing a computer system, having at least a processor, memory, and touchscreen, to create a hibernatable virtual pointing device. The method includes the steps of creating a virtual pointing device on the touchscreen under at least a first portion of a hand positioned in a first location on the touchscreen, whereby a hand behavior over the virtual pointing device causes a command to be invoked, in response to detecting the hand no longer being positioned on the touchscreen, placing the virtual pointing device in hibernation and, in response to detecting the hand being re-positioned at a second location on the touchscreen, moving the virtual pointing device to the second location and bringing the virtual pointing device out of hibernation, whereby the hand behavior over the virtual pointing device causes the command to be invoked.

Abstract: A method of providing a dynamic abstraction layer, such as a boot filesystem, for a computer having a particular hardware platform, in order to make a basic operating system more portable. The method includes storing the dynamic boot filesystem in a protected space in the computer before the normal boot sequence, and then retrieving the dynamic boot filesystem from the protected space during the boot sequence and loading the retrieved dynamic boot filesystem. The computer firmware first loads a simulated boot image which contains the dynamic boot filesystem, and then loads an operating system boot image which contains the operating system and instructions for retrieving the dynamic boot filesystem. A default boot filesystem may be used if no previously stored dynamic boot filesystem is found. In a UNIX embodiment, the dynamic boot filesystem includes a hardware-dependent PAL (Portable Assist Layer).

Abstract: A method and system are disclosed in a first data processing system for processing a first instruction in response to an initiation of processing of a second instruction in an emulation environment. The first data processing system includes a first architecture, a first processing environment, and an emulation environment. The first instruction is executable within the first processing environment. The emulation environment is generated by the first architecture. The emulation environment emulates a second data processing system. The second data processing system includes a second architecture and a second processing environment. The second instruction is executable within the second processing environment. A file is established within the emulation environment. The file includes a plurality of routines. Each routine is associated with one of the second plurality of instructions. One of the routines is associated with the second instruction.