Abstract: A dielectric layer (27) is formed between a semiconductor surface (24) and an electrical contact (26) to promote adhesion of the contact (26). The dielectric layer (27) is formed by cleaning operation followed by a chemical oxidation.

Abstract: A variable capacitance semiconductor device (10) such as a varactor diode, is formed to have a plurality of openings (13), such as a plurality of trenches, that cause the depletion regions (16) to overlap. This overlap results in a rapid change of capacitance for a given change of voltage, and allows efficient operation over a small voltage range.

Abstract: A Pulse Width Modulation (PWM) control circuit is used in a switched-mode power supply (SMPS) having a normal mode and a standby mode, for controlling and regulating the SMPS. An input of the PWM control circuit is arranged to receive a signal indicating an amount of current supplied by the supply. An over-current determining arrangement provides an over-current signal in the event of there being an over-current condition in the signal indicating the amount of current supplied by the supply. A further input of the PWM control circuit receives a regulation signal in the event of there being a regulation output from circuitry coupled to receive power from the SMPS. A logic circuit within the PWM control circuit compares the over-current signal and the regulation signal in order to determine whether the switched-mode power supply is in standby mode or normal mode, thus avoiding the need for a dedicated control pin to indicate standby and normal modes.

Abstract: A semiconductor device (10) having a termination structure (25) and a reduced on-resistance. The termination structure (25) is fabricated using the same processing steps that were used for manufacturing an active device region (21). The termination structure (25) and the active device region (21) are formed by etching trenches (22, 23) into a drift layer (14). The trenches (22, 23) are filled with a doped polysilicon trench fill material (24), which is subsequently planarized. The semiconductor device (10) is formed in the trenches (22) filled with the polysilicon trench fill material (24) that are in the active region. The trenches (23) filled with the polysilicon trench fill material (24) in a termination region serve as termination structures.

Abstract: A method and circuit for reducing the leading edge spike in a current sense signal. The current sense signal is a measure of the current through a switched power device controlled by a switching regulator controller. The slew rate of the current sense signal is limited to prevent the slew rate from exceeding a predetermined maximum. The limited slew rate signal is provided to the switching regulator controller. A transconductance amplifier may be used to limit the slew rate of the current sense signal. A capacitor at the output of the transconductance amplifier contributes to controlling the maximum slew rate of the amplifier. The capacitor is charged by the current output of the amplifier to provide a voltage signal for use in place of the original current sense signal. A switch may be provided for selecting between the slew rate limited current sense signal and the original current sense signal.

Abstract: A method of manufacturing a semiconductor component includes providing a semiconductor substrate (200) having top and bottom surfaces, forming a drain electrode (160) at the bottom surface of the semiconductor substrate (200), and simultaneously forming source and gate electrodes (251, 254, 255, 253) at the first surface of the semiconductor substrate (200).

Abstract: A power factor correction controller circuit 100 for controlling the duration of each on time phase and off time phase of a switched inductor power factor correction circuit 20, 30, 40, 50, 100 which is adapted for use with a rectifying arrangement 9, 10, 60, 70 producing a substantially regulated output voltage, Vo. The controller circuit 100 comprises an input terminal 114 for receiving a signal representative of Vo; an output terminal 131 for outputting a signal representative of the duration of each on time phase and off time phase; and on time determination means 110, 111, 112, 113, 114, 115, 116, 117; wherein the on time determination means acts to vary the maximum duration of each on time phase in an inverse dependence on Vo.

Abstract: A method of manufacturing an electronic component includes providing a substrate (101), forming a semiconductor device in the substrate (101), depositing a metal layer (107) over the substrate (101) and electrically coupled to the semiconductor device, depositing a layer (108) of solder over the metal layer, and wire bonding a wire (109) to the metal layer (107).

Abstract: A load driver circuit (10) includes an output driver (11) suitable for driving an inductive load (13). An output clamp circuit (15) clamps the output (12) to a high voltage during turn-off of the output driver (11). An open load detect circuit (26) clamps the output (12) to a lower voltage when the load (13) has an open circuit fault. A power fault voltage detect circuit (28) clamps the output (12) to another low voltage during a power fault condition.

Abstract: A switching power supply (10) uses a switching regulator (18) that is capable of operating in a dual mode with either primary side regulation or secondary side regulation. The primary and secondary side regulation schemes generate opposite phase feedback signals. The switching regulator has first (56, 62) and second (70, 74) detectors on the feedback input which detect when the feedback signal is less than a first value and also detect when the feedback signal is greater than a second value. By monitoring either case, the switching regulator can enable and disable a gate drive signal in response to opposite phases of the feedback signal and thereby regulate the switching power supply.

Abstract: A semiconductor device (10) uses a plurality of floating field conductors (26, 28) to provide a substantially uniform electric field along the surface of the drift region (17) of the device (10). This substantially uniform electric field increases the breakdown voltage per unit length of the drift region (17).

Abstract: A method of manufacturing a semiconductor component includes applying an encapsulant (211) to a wafer (210, 430), degassing the encapsulant (211), and separating the wafer (210, 430) into a plurality of semiconductor components. Manufactured in this manner, the encapsulant (211) of the semiconductor component is substantially devoid of air bubbles and voids.

Abstract: A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.

Abstract: An electronic component includes a substrate (301, 801), a leadframe (101, 601, 710) coupled to a first surface of the substrate (301, 801) and extending beyond the first surface and towards a second surface of the substrate (301, 801), and an electrically conductive layer coupled to the second surface and coplanar with a contact portion of the leadframe (101, 601, 710) where the leadframe (101, 601, 710) and the electrically conductive layer form a package around the substrate (301, 801).

Abstract: A wireless, peer-to-peer, capability addressable network (22) is disclosed. The network (22) accommodates any number of peers (20). Network connections are formed based upon proximity between peers (20) and upon a needs and capabilities evaluation (82). Networks (22) support three classifications of service capabilities: service requesting, service providing, and service relaying. Wireless communications occur at a sufficiently low power to form a detection zone (28) of less than five meters for many peers (20).

Abstract: A method of packaging a semiconductor device (10) partitions a distribution substrate (20, 40) into regions (31-34) such that attachment points (22) for electrically coupling to the semiconductor device lie in a first region (31). A first set of conductors are routed from a portion of the attachment points to terminals in a second region (32). Another portion of the attachment points are assigned to available routing channels of the second region for disposing a second set of conductors across the second region to a third region (33). Partitioning improves routing efficiency without requiring objects to be located on grid points or restricting the angles of the routing channels.

Abstract: A temperature detection circuit that minimizes the influence of variations due to manufacturing process and other factors, and can be used at high temperatures near its maximum usable temperature. According to the present invention, a temperature detection circuit is provided which comprises: a first current source coupled to a detection node; a second current source coupled in series to the first current source, and coupled to the detection node, the second current source having a temperature coefficient different from that of the first current source; and a detector coupled to the detection node.

Abstract: An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.

Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a gate structure (27) formed on the semiconductor substrate (11). A source region (23) and a drain region (24) are formed on the semiconductor substrate such that the source region (23) and the drain region (24) are laterally spaced apart from the gate structure (27).

Abstract: A system for laying out a capacitor array (400) implements a programmable capacitor (33-39) whose operation is controlled with a binary control word. A programmable capacitance is produced by coupling binary weighted, switchable capacitors (101-107) between terminals (51, 52) of the programmable capacitor. The capacitor array includes two or more unit capacitors (101, 103) of unequal areas. The other capacitors in the array are derived by interconnecting multiple capacitors that match one of the unit capacitors. Die area is reduced while accuracy is maintained by controlling the larger unit capacitor with the least significant bit of the binary control word whenever possible and using the smaller unit capacitor only as a trim capacitor.