Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract: A circuit structure for reading data contained in an electrically programmable/erasable integrated non-volatile memory device includes a matrix of memory cells and at least one reference cell for comparison with a memory cell during a reading phase. The reference cell is incorporated in a reference cells sub-matrix which is structurally independent of the matrix of memory cells. Also provided is a conduction path between the matrix and the sub-matrix, which path includes bit lines of the sub-matrix of reference cells extended continuously into the matrix of memory cells.

Abstract: A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.

Abstract: The electronic ignition device includes an ignition coil with a primary winding terminal and a secondary winding terminal generating a spark, a power element arranged between the primary winding terminal and ground, a protection circuit issuing a disable signal to the control terminal of the power element in preset conditions, and a voltage limiting circuit having inputs connected to the primary winding terminal and to the battery voltage, and an output connected to the control terminal of the power element. The voltage limiting circuit detects a potential difference between its own inputs and supplies to the control terminal an activation signal for the power element, in presence of the deactivation signal and when the potential difference exceeds the supply voltage by a preset value. Thereby, the voltage limiting circuit limits the voltage on the primary winding terminal to a preset value which depends upon the value of the battery voltage.

Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.

Abstract: The invention relates to a process for manufacturing a light sensor device in a standard CMOS process, including, implanting active areas on a semiconductor substrate to obtain a first integrated region of a corresponding photosensor; and forming a stack of layers having different thickness and refractive index layers over the photosensor to provide interferential filters for the same photosensor. At least one of the above mentioned layers is formed by a transparent metallic oxide having a high refraction index and a corresponding high dielectric constant. In this manner, due to the transparency of the high refraction index material, the design of interferential resonators is rendered more flexible making possible the use of a stack of layers including more than one high refraction index layer.

Abstract: A circuit to control the supply of a reactive load, for supplying variable quantities of energy to the load in a predetermined manner is included in a system. The system also includes reactive components which are connected to the load by way of a controllable electronic switch and which form a resonant circuit with the load when the electronic switch is closed. Further, the system includes a circuit for activating the electronic switch, and a control unit which coordinates the operation of the controlled supply circuit and of the activation circuit in accordance with a predetermined program. The system enables the load to be driven with a particularly low power dissipated.

Abstract: A current control method controls current for drive systems of multi-phase brushless motors, in particular at phase switching, wherein the motor coils coupled to a common node are driven by applying a respective drive voltage to the free end of each coil via corresponding power stages. The method comprises switching the current flow from one phase to the next in the direction of rotation of the motor at the phase switch, thereby forcing the unaffected one of said coils by the phase switch into a state of high impedance. Advantageously, the decreasing rate of the current in the coil unaffected by the phase switch can be twice as high as the decreasing rate of the current in the phase being switched from.

Abstract: The equivalent computational precision in an associative memory is increased by determining the difference between the bit precision that is required in order to represent a given number in the memory and the bit precision that can be represented in a memory element of the memory, which is dictated by the inherent characteristics of the memory; determining, on the basis of the difference, the number of memory elements of the memory required in order to represent the given number with the required bit precision; and dividing the given number over the number of memory element of the memory, determining a base value to be loaded into the number of memory element and a remainder which indicates a subset of the number of memory element of the memory over which the remainder is to be divided.

Abstract: A method corrects the errors in a multilevel memory, by increasing the number of levels of the memory cells, instead of adding further memory cells. In other words, the present correction method is based on the principle of storing, in each multilevel memory cell, instead of a whole number b of bits in the binary word to be stored, data units which are correlated to this binary word, and are expressed in a numerical base other than binary, and not a power of two. This is carried out by converting the binary word with m bits to be stored, from the binary base, to a base n, which is not a power of two, and by associating with the converted word a correction word, which is also formed from digits with a base n; the digits of the converted and correction words are then each stored in a respective multilevel memory cell, with a number of levels which is equivalent to the numerical base used for the conversion.

Abstract: A control device for a focusing system of a compact disk (CD) reader is provided. The control device uses fuzzy logic incorporated to the audio data processing system of the CD reader which is adapted to detect and segregate a light beam reflected by the surface of the compact disk from an incident light beam to the surface. The fuzzy logic control device receives a focus error signal and a derivative of the focus error. It then calculates, using appropriate membership functions, output signals to provide to a focusing servo-system of the CD reader to adjust the distance of the focal plane from the light beam detecting circuitry.

Abstract: A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a preceding clock period. The accumulator also includes at least one second stage having incrementer/decrementer means for performing an increment, decrement or identity operation on a most significant part of the output of the accumulator. The incrementer/decrementer means includes logic means for triggering the increment, a decrement or identity operation on the most significant part of the accumulator output based on a decision made on results obtained at the previous clock period.

Abstract: The invention relates to a method of producing a multi-level memory of the ROM type in a CMOS process of the dual gate type. Specifically, some of the transistors of the ROM cells have their polysilicon layers masked and the ROM cells are then implanted by a first dopant species in the active areas of the exposed transistors. Then the masks are removed from the polysilicon layer, and a second dopant species is implanted in said previously covered layer.

Abstract: A method of modifying the threshold voltages of a plurality of non-volatile memory cells, for example, flash EEPROM memory cells, after an erasure operation, is described. In order to perform the equalization quickly and to optimize the use of the voltage supplies for biasing the columns, the method provides for the following steps: connecting all of the column lines to a voltage supply, monitoring the supply voltage, and applying, to all of the row lines, a voltage variable from a predetermined minimum value to a predetermined maximum value, the rate of change being regulated to maintain the supply voltage of the column lines at a substantially constant, predetermined value. The same method can be used for reliable and quick programming of a memory of the flash EEPROM type, or of another type.

Abstract: A circuit device structured to enable a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and including a matrix of memory cells with sectors organized into columns, wherein each sector has a group of local word lines individually connected to a main word line running through all of the matrix sectors which have rows in common is presented. The device includes a PMOS first transistor having conduction terminals connected respectively to the main word line and the local word line, an NMOS second transistor having conduction terminals connected respectively to the local word line and the main word line, and a PMOS third transistor having conduction terminals connected respectively to the main word line and the local word line. Such a third transistor is a charge transistor that reduces the charging time for the local word line.

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract: A microelectromechanical structure includes a rotor element having a barycentric axis and suspended regions arranged a distance with respect to the barycentric axis. The rotor element is supported and biased via a suspension structure having a single anchoring portion extending along the barycentric axis. The single anchoring portion is integral with a body of semiconductor material on which electric connections are formed.

Abstract: A Switched Reluctance Motor or SRM is controlled by detecting signals indicating the angular position of the rotor of the motor and energizing the motor depending on these signals. The periods of the abovementioned signals are discretized into a given number of time windows, defining a table with a plurality of positions each corresponding to one of said time windows. A respective power supply configuration of the motor is associated with each of said positions of the table. The positions in the table undergo cyclical scanning and the motor is energized with the power supply configuration associated with the position identified in each case during the scanning movement. The scanning movement is performed from a reference position identifying the energization advance of the motor and preferably determined using a logic of the fuzzy type based on the speed of rotation and the load of the said motor.

Abstract: A circuit structure for programming data in reference cells of an electrically programmable/erasable integrated non-volatile memory device includes a matrix of multi-level memory cells and a corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell is incorporated, along with other cells of the same type, in a reference cell sub-matrix which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix branch off to a series of switches which are individually operated by respective control signals REF(i) issued from a logic circuit with the purpose of selectively connecting the bit lines to a single external I/O terminal through a single addressing line of the access DMA mode.