Abstract: A NAND gate circuit system that provides for adjustable pulse width that comprises eight transistors arranged so that a signal can propagate through the transistors in series, the transistors consisting of at least one N-channel and at least one P-channel transistor.

Abstract: A leadframe has a bus bar extending between two lead fingers on the leadframe. The bus bar and lead fingers are etched to reduce the thickness thereof, and the bus bar is folded under the lead finger, but insulated therefrom by a strip of insulating material. An adhesive is applied to the bus bar to attach it and the leadframe to the surface of a semiconductor chip.

Abstract: A method and circuitry are provided for controlling voltage in an electronic circuit. Sensing circuitry coupled to an output node senses a rate of change in an output voltage of the output node and outputs a signal in response thereto. Amplification circuitry coupled to the sensing circuitry receives the signal and outputs an amplified signal in response thereto. Modification circuitry coupled between the amplification circuitry and the output node receives the amplified signal and modifies the rate of change in response to the amplified signal.

Abstract: A system and method for polishing the edges of a plurality of semiconductor wafers rotates a stack of wafers against a polish one or more pads such that both the wafer edges and the sides of the edges are polished to a mirror finish. The polish pad has a series of grooves through which the wafer edges are passed to polish the sides of the wafer edges, or two pads are used, one with grooves and one without grooves.

Abstract: A multi-mode digital to analog converter for converting a digital input into an analog voltage according to a linear or a companding transfer function. The converter comprises a charge redistribution device for creating an analog voltage at a node and switching circuitry for controlling the charge redistribution device. The switching circuitry is operable to effect either transfer function responsive to its inputs.

Abstract: A decoder for a memory redundancy scheme is disclosed which allows replacement of a number of memory cell locations in connection with the state of a plurality of fuses.

Abstract: The invention is to a method for plasma spraying a ceramic or plastic material on selected areas of leads to form stabilizer/spacers for the leads.

Abstract: A method of processing a semiconductor wafer using a wafer chuck having a first end with a non-planar surface, the non-planar surface shaped such that a wafer supported at a plurality of points about its periphery will have a uniform pressure between its surface and the non-planar surface, and pressing a surface of the wafer against the non-planar surface of the wafer chuck.

Abstract: Circuitry (46, or 28 and 70) for thermally separating a power integrated circuit device (12) from a plurality of other such devices (14, 16, and 18) on a common power integrated circuit chip (10) operate when the device (12) reaches a thermal shutdown temperature setpoint (56) with an output current at a predetermined current limit (54). The circuitry 46, or 28 and 70 switches the output current to a shutdown current level (57) until the device (12) reaches a predetermined lower temperature setpoint (58). Circuitry (46, or 28 and 70) restores the output current level to the predetermined current limit only after the device (12) reaches both the predetermined lower temperature setpoint (58) and a predetermined circuit setpoint (62 or 74). The circuit setpoint (62 or 74) associates with the temperature of the device (12) and may be either a yet lower temperature setpoint (62) or a specified time delay (74).

Abstract: A method and system for semiconductor wafer cleaning within a condensed-phase processing environment (54) is based on first cooling the semiconductor wafer (52) to a predetermined temperature in order to condense a liquid film (156) on the semiconductor wafer surface from a condensable process gas or gas mixture. Then, the method and system promote thermally activated surface reactions and rapidly evaporate liquid film (156) from the semiconductor wafer surface using a high peak power, short pulse duration energy source such as a pulsed microwave source to dissolve surface contaminants and produce drag forces sufficiently large to remove particulates (154) and other surface contaminants from the surface of the semiconductor wafer. The method and system of this invention can remove various organic, metallic, native oxide, and particulate contaminants from semiconductor wafer surface.

Abstract: A modeling system 10 comprises a central processing unit 12 coupled to an arithmetic logic unit 16. A device testing system 18 is used to empirically analyze the operational characteristics of a transistor to be modeled by the system 10. A set of parameter values are stored in a memory circuit 14 coupled to central processing unit 12. An input and display system 20 is used to interact with the central processing unit 12. The central processing unit 12 uses the arithmetic logic unit 16 to calculate an objective function which is essentially a measure of the error between the measured values of operating variables of the device to be modeled and theoretical values of the operating variables calculated using initial guesses of modeling parameters. The objective function is minimized by calculating the gradient of the objection function to obtain a next guess point with its associated parameter values.

Abstract: A redundancy scheme for a memory is disclosed which allows defect correction, particularly, word line to word line short correction through the use of a minimal number of redundant lines. The scheme makes use of some logical function of the non-matching address bits of two word lines between which a word line to word line short exists. The logical function can comprise the exclusive OR, or some function of the exclusive OR (i.e. exclusive NOR of the non-matching address bits of two word lines between which a word line to word line short exists.

Abstract: The present invention includes a device (10) that accepts separately referenced signal levels at a single input. The device (10) receives an input signal at a latch (12), a translator circuit (14), and an input follower circuit (16). The latch (12) activates either the translator circuit (14) or the input follower circuit (16) depending upon the referenced signal level at the input signal. When activated, the translator circuit (14) converts a first referenced signal level into a signal referenced to the supply voltage level of the device (10). The input follower circuit (16) converts a second referenced signal level into a signal having a supply voltage referenced signal level. An output circuit (18) receives the signal from the appropriately activated circuit and generates an output signal referenced to the supply voltage of the device (10).

Abstract: A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

Abstract: A multi-zone multi-electrode plasma processing method for uniform plasma processing and effective in-situ fabrication reactor process chamber (10) cleaning during a plasma deposition or etch process first comprises the steps of flowing plasma deposition or etch gases into the process chamber (10) in a chopped or continuous mode (line 214) followed by flowing plasma gases into the process chamber (10) in a chopped mode (220) or a continuous mode. By intermittently activating (224) at least one plasma electrode (24 or 52) upon initiating flow of the plasma processing gas, the method generates a process plasma medium to perform the plasma-enhanced deposition or etch process. Additionally, intermittently activating the same or a different configuration of plasma electrodes (66), during the time that the process gas flows are stepped, an in-situ cleaning plasma is produced for performing a plasma-assisted chamber cleaning process.

Abstract: A processing apparatus and method wherein a wafer is exposed to activated species generated by a first plasma which is separate from the wafer, but is in the process gas flow stream upstream of the wafer, and is also exposed to plasma bombardment generated by a second plasma which has a dark space which substantially adjoins the surface of the wafer. The in situ plasma is relatively low-power, so that the remote plasma can generate activated species, and therefore the in situ plasma power level can be adjusted to optimize the plasma bombardment. Ultraviolet light to illuminate the face of a wafer being processed is generated by a plasma which is within the vacuum chamber but is remote from the face of the wafer. It is useful to design the gas flow system such that the ultraviolet-generating plasma has its own gas feed, and the reaction products from the ultraviolet-generating plasma do not substantially flow or diffuse to the wafer face.

Abstract: An antifuse (42) is formed by forming a layer of titanium tungsten (34) overlying a portion of a first metal layer (28). The titanium tungsten layer (34) is oxidized to form a film of oxide (36) on its surface. Insulating regions (30) are formed adjacent the titanium tungsten layer (34) and overlying the first metal layer (28). A second metal layer (40) is formed overlying the titanium tungsten layer (34). Applying a break down voltage across the first and second metal layers (28), (40) will break down the oxide film (36), thereby causing a connection between the first and second metal layers (28), (40).

Abstract: A chip-on-board assembly and a method of making is described in which semiconductor chips having center contacts are mounted active side down on the circuit board, with the center contacts centered in an elongated opening in the circuit board. The center contacts are connected through the openings in the circuit board to contacts on the circuit board on the opposite side of the circuit board on which the semiconductor chip is mounted. Semiconductor chips are alternately mounted on opposite sides of the circuit board to provide a higher placement density of semiconductor chips.

Abstract: A vertical lead-on-chip package and the method of making defines a high density array of semiconductor devices with leads extending from and across one face of the device, to the edge of the device such that a plurality of devices are vertically mounted on a circuit board. Each device has a heat sink thereon which is held in a fixture which serves as an array heat sink during testing and burn-in and during mounting and operation of the devices on the circuit board.

Abstract: A multiple range amplifier capable of providing a large number of ranges with great accuracy is provided by a circuit free of discrete resistors and which includes two inverting operational amplifiers and two, two-quadrant multiplying DACs which are externally controllable. The output of the first inverting amplifier is fed back through the first DAC and is also fed through the second DAC to the second inverting amplifier. Each of the DACs is externally controllable to provide the desired range with great precision. The gain of the system is the product of the gain of the two amplifiers. Also, a programmable filter is provided to optimize system performance, for example, in the removal of noise. This is accomplished by providing a fundamental filter circuit having an operational amplifier, a two quadrant multiplying DAC, a capacitor and several resistors. The output of the operational amplifier is fed back to the input via a capacitor and a DAC input control circuit and an RC circuit.