Abstract: A lithographic system with improved control of critical dimensions (CD). The lithographic system includes a detector for determining the amount of energy absorbed by the photoresist. This enables the lithographic system to expose each field with the required exposure dose, thus reducing variations in CD.

Abstract: An improved process for preparing nitrogen containing substrates selected from the group consisting of silicon oxynitride, silicon nitride and titanium nitride films and silicon dioxide cap films characterized by prevent resist contamination when used as dielectric anti-reflective coatings, using a high density plasma CVD system, comprising: providing a processing chamber holding a wafer in a vacuum sufficient to enable O.sub.2 to be used as an oxygen source without risk of explosion in a plasma generating region of the processing chamber; introducing a gaseous mixture selected from the group consisting of SiH.sub.4 /O.sub.2 /N.sub.2 or SiH.sub.4 /O.sub.2 /N.sub.2 /Ar into the processing chamber; and subjecting the processing chamber to a RF electrical signal of sufficient frequency to create a high density plasma in the plasma generating region of said processing chamber, whereby said wafer is processed by resulting high density plasma generated by said RF electrical signal.

Abstract: A method and apparatus for protecting a neighboring area that is adjacent to a first area that is to be etched. The method includes creating a guard cell substantially surrounding the first area, but excluding the neighboring area. The guard cell is formed of a material that is substantially selective to the etch process subsequently employed to etch within the first area. After the guard cell is formed, an etch is performed within the first area, while the guard cell prevents etching of the neighboring are outside the guard cell.

Abstract: A method of forming very small diameter metal lines in a dielectric layer 12 comprising forming an opening in the dielectric layer using photolithographic techniques, filling the opening with an insulating material 16 and planarizing the dielectric layer using chemical metal polishing techniques, which are continued so as to form small trenches 17 in the dielectric material on either side of the insulating material, filling in the trenches with metal and planarizing the metal layer using chemical metal polishing.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

Abstract: A multi-level integrated circuit metalization system having a composite dielectric layer comprising a layer 22 of diamond or sapphire. A plurality of patterned metalization layers is disposed over a semiconductor substrate 10. A composite dielectric layer is disposed between a pair of the metalization layers. The composite dielectric layer 22 comprises a layer of diamond or sapphire. The diamond or sapphire layer has disposed on a surface thereof one of the patterned metalization layers. A conductive via 34 passes through the composite layer. One end of the conductive via is in contact with diamond or sapphire layer. The diamond or sapphire layer conducts heat laterally along from the metalization layer disposed thereon to a heat sink provided by the conductive via. The patterned diamond or sapphire layer provides a mask during the second metalization deposition.

Abstract: A calibrated Delay Locked Loop (DLL) arrangement synchronizes an output data signal thereof to an input clock signal. A delay line receives the input clock signal and generates a clock output signal having a selective delay. A gating circuit receives the clock output signal and separately generates an imitation data signal that corresponds to the clock output signal, and latches an input data signal with the output clock signal to generate an output data signal. The gating circuit is also responsive to a switching control signal having a first logical value for providing only the output data signal to an output thereof, and to the switching control signal having a second logical value for providing only the imitation data signal to an output thereof. A driver receives the gating circuit output signal and provides this signal as the calibrated DLL arrangement output data signal.

Abstract: A phase shifting mask having an alignment region, a plurality of first transparent regions, and a plurality of transparent phase shifting regions. The mask includes a transparent substrate having an opaque material disposed on selected portions of a surface of the substrate. The opaque material disposed on a first portion of the surface of the substrate has a cross-shaped space therein to expose an underlying portion of the surface of the substrate. A first line of the cross-shaped space provides a first one of a pair of first alignment detection indicia for the alignment detection region. A second line of the cross-shaped space provides a second one of a pair of first alignment detection indicia for the alignment detection region. The opaque material disposed on each one of a pair of second portions of the surface of the substrate has a plurality of spaces therein. Each one of the spaces in the second regions exposes a underling portion of the surface of the substrate.

Abstract: A method for processing a semiconductor substrate to form a denuded zone therein. The method includes providing a semiconductor substrate having an oxygen concentration in a region of the substrate adjacent to a surface of such substrate. A trench is formed in the surface of the substrate. Subsequent to the formation of the trench, reducing the oxygen concentration within the region.

Abstract: A method for manufacturing a dual damascene structure includes the use of a sacrificial stud and provides an improved defined edge on the interface between the conductive line openings and the via openings.

Abstract: A multi-bit trench capacitor having first and second storage nodes provided in the lower region thereof is described. The storage nodes are separated by a dielectric layer that separates the sensing voltage into upper and lower ranges corresponding to data stored in the first and second storage nodes.

Abstract: Improved techniques for driving wordlines of a semiconductor memory device are described. Accordingly to the invention, a wordline 402 is driven by a wordline driver 406 at a first end and then provided with a small amount of additional circuitry 442 at the other end of the wordline. When the additional circuitry senses that the wordline is beginning to transition to an active state, the additional circuitry operates to assist or accelerate the transition of the wordline to the active state. Accordingly, the invention operates to rapidly transition wordlines to an active state while using only minimal amounts of die area. The invention is particularly well suited for dynamic random access memories.

Abstract: Reduction of black silicon is achieved by providing a dielectric layer in at least the bead region of the wafer before the formation of a hard etch mask.

Abstract: An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).

Abstract: Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

Abstract: A method for fabricating a bit line junction in a DRAM array device which improves the doping profile in the channel region. The method includes contradoping via ion implantation through the bit line contact opening made in the device during processing. This particular doping method increases the concentration of dopants in the channel region on the bit line side of the array, without a corresponding increase of dopants on the buried strap side. Such a doping profile results in an improvement in the off current behavior of the device. Depending on the aspect ratio of the contact opening, tilt angles for the ion implantation are possible and can be adjusted for maximum off current efficiency.

Abstract: The photolithographic etching of contact holes in trenches in an insulator layer over a silicon body is improved by adjusting properly the depth of the trench and the thickness of the photoresist used in the photolithography.

Abstract: A hard etch mask comprising phosphorus doped silicate glass for reactive ion etching of a substrate to form trenches therein.

Abstract: A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.