Abstract: A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3.times.3 block of the first pads.

Abstract: Healing of scratches created during CMP is achieved by reflowing the material containing the scratches and then depositing a top layer of material. The deposition of the top layer further enhances the healing of the scratches.

Abstract: A memory circuit having a stitched architecture wherein word lines of the memory circuit comprise a low resistance conductor stitched to a gate conductor portion having a higher resistance than the low resistance conductor. The memory circuit includes an array of memory cells having thereon bit lines disposed generally along a first direction and the word lines disposed generally along a second direction substantially orthogonal to the first direction. The memory circuit also includes an array sense amplifier region disposed adjacent the array of memory cells generally along the first direction. The array sense amplifier region has therein a plurality of array sense amplifiers coupled to the bit lines. The memory circuit further includes a stitch region containing contacts for stitching the low resistance conductor with the gate conductor. The stitch region is disposed adjacent the array of memory cells generally along the second direction.

Abstract: Improved technique of forming trench capacitors without causing excessive erosion at the edges of the array region resulting from polishing. The erosion is reduced by providing a block mask to protect the array region while partially removing a portion of the hard mask used to etch the trenches in the field region. The partial etch equalizes the height of the hard mask in the array and field region after formation of the deep trenches by a reactive ion etch.

Abstract: A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

Abstract: Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.

Abstract: In preparation for etch processing a semiconductor chip having areas of little or no pattern and areas that are heavily patterned, adding non-operative patterns to the areas having little or no pattern so that the overall pattern density is about the same across the chip.

Abstract: A method for fabricating an electrically blowable fuse on a semiconductor substrate. The method includes forming a fuse portion 102 on the semiconductor substrate. The fuse portion is configured to turn substantially non-conductive when a current exceeding a predefined current level passes through the fuse portion. The method also includes depositing a substantially conformal first layer 302 of dielectric material above the fuse portion and depositing a second layer 304 of dielectric material above the first layer, thereby forming a protrusion of dielectric material above the fuse portion. The second layer being different from the first layer. The method further includes performing chemical-mechanical polish on the protrusion to form an opening through the second layer above the protrusion. There is also included etching, in a substantially isotropic manner, a portion of the first layer through the opening to form a microcavity 502 about the fuse portion.

Abstract: Method for forming three-dimensional device structures comprising a second device having sub-groundrule features formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device. the sub-groundrule feature is formed using mandrel and spacers.

Abstract: A method for forming a bottle shaped trench 20 in a semiconductor substrate 10 includes reactive ion etching a trench having a tapered top portion 25 in the semiconductor device and continuing to reactive ion etch while increasing the temperature of the semiconductor device to impart a reentrant profile 22 to the trench.

Abstract: An OCD circuit with stacked transistor that is gated to switch on prior to the switching on of the transistors which the stacked transistor protects. The gating of the stacked transistor results in the reduction of the total OCD output capacitance.

Abstract: A polishing pad conditioner and a method for conditioning a polishing pad of a chemical/mechanical polishing system. The polishing pad conditioner includes a body defining an upper surface and a lower surface; at least one conditioning element mounted at the lower surface of the body, the conditioning element including a conditioning surface and an opening adjacent the conditioning surface; and a vacuum source operatively connected to the opening in the conditioning element. The method for conditioning a polishing pad includes the steps of holding a polishing pad conditioner including a conditioning element, a conditioning surface thereon and an opening in the conditioning element adjacent the conditioning surface in contact with a surface of the polishing pad; applying a vacuum source to the pad, the vacuum source being operatively connected to the conditioning element; and conditioning the surface of the polishing pad while simultaneously vacuuming particles therefrom.

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Abstract: A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.

Abstract: A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. An MDQ switch being located in a sense amplifier region occupying a corresponding row-wise space to the at least one driver to provide space efficient placement thereof.

Abstract: An equalizer circuit for precharging a pair of bit lines in a dynamic random access memory circuit. The equalizer circuit includes a substantially T-shaped polysilicon gate portion oriented at an angle relative to the pair of bit lines. The angle is an angle other than an integer multiple of 90.degree.. The substantially T-shaped polysilicon gate portion includes first polysilicon area for implementing a gate of a first switch of the equalizer circuit. The first switch is coupled to a first bit line of the pair of bit lines and a second bit line of the pair of bit lines. The substantially T-shaped polysilicon gate portion also includes a second polysilicon area for implementing a gate of a second switch of the equalizer circuit. The second switch is coupled to the first bit line of the pair of bit lines and a precharge voltage source. The substantially T-shaped polysilicon gate portion further includes a third polysilicon area for implementing a gate of a third switch of the equalizer circuit.

Abstract: Method and apparatus are provided for determining a warpage of a wafer (14) for providing a minimum clamping voltage to an electrostatic chuck (ESC) when the wafer is subsequently processed thereon. The apparatus includes an electrostatic chuck (12, 120) and a control arrangement (16, 18, 20). The electrostatic chuck includes a clamping surface (13, 130) for clamping a wafer thereto by a clamping force that is dependent on a clamping voltage applied to the electrostatic chuck. The control arrangement is used to detect an inherent warpage in the wafer prior to a processing of that wafer, and determine a minimum clamping voltage from the measured warpage that is to be applied to the electrostatic chuck during a subsequent processing of the wafer. The minimum clamping voltage has a value for each wafer that securely clamps the wafer to the clamping surface and avoids excessive warpage and backside abrasion of the wafer.

Abstract: Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate. By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.

Abstract: An improved oscillator circuit 400 having a frequency that is substantially independent of temperature. The improved oscillator circuit is particularly well suited for use in an integrated circuit device to produce a clock signal, such as a refresh clock for a dynamic random access memory (DRAM) integrated circuit. The current i.sub.c produced is temperature independent so that the refresh frequency for the DRAM integrated circuit is stable over temperature.

Abstract: A method in a plasma processing chamber for improving oxide-to-nitride selectivity while etching a borophosphosilicate glass (BPSG)-containing layer to create a self-aligned contact on a semiconductor substrate. The (BPSG)-containing layer is disposed on a SiN layer and into a via formed through the SiN layer. The method includes placing the substrate into the plasma processing chamber, and flowing an etchant source gas into the plasma processing chamber. The etchant source gas includes C.sub.4 F.sub.8 and an additive gas other than carbon monoxide (CO). The additive gas includes molecules having both oxygen atoms and carbon atoms in a 1:1 ratio. The method further includes exciting the etchant source gas with a radio frequency (RF) power source having a frequency of 13.56 MHz to strike a plasma from the etchant source gas, thereby etching at least partially through the BPSG-containing layer.