Abstract: A random access memory cell having a trench capacitor formed below the surface of the substrate. A shallow trench isolation is provided to isolate the memory cell from other memory cells of a memory array. The shallow trench isolation includes a top surface raised above the substrate to reduce oxidation stress.

Abstract: A substrate cleaning assembly (10) and method for removing contaminant substances (11) from a surface (12) of a substrate (13) employed in microelectronics manufacturing. The cleaning assembly (10) includes a substance locator (15) adapted to locate and map at least one contaminant substance (11) on the surface (12) of the substrate (13) and a dispenser (16) formed and dimensioned to accurately dispense a substantially controlled, impinging stream (17) of cleaning agent along a path (18). A controller (20) is coupled to the map device (15) and the dispenser (16), and is adapted to control the impinging stream (17) such that the located contaminant substance (11) is positioned in the path (18) of the impinging stream (17) to enable substantially localized impingement and removal of the substance (11) from the substrate surface (12).

Abstract: The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.

Abstract: Disclosed is a semiconductor memory having a main memory cell array and redundant memory cells, with a plurality of fuses that can be physically separated from their associated fuse latches. Physical separation is possible by incorporating serial transfer circuitry to serially transfer fuse data from the fuses towards the latches. As a result, only a small number of wires are needed to connect the fuses to the fuse latches, allowing for flexible fuse placement within the memory.

Abstract: A complex building agent, such as EDTA is added in a predetermined concentration to the "SC 1" step of a "PIRANHA-RCA" cleaning sequence for reducing the metal contamination left on the surface of a silicon wafer after completion of this cleaning step.

Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer.

Abstract: A method of forming aluminum contacts of submicron dimensions wherein, after formation of both vias and line openings in a silicon oxide layer, a metal stop layer is deposited, followed by deposition of aluminum. Alternatively, the metal stop layer is deposited prior to forming the vias and line openings. The excess aluminum is removed by chemical-mechanical polishing, the stop layer providing high selectivity to the chemical mechanical polishing. The stop layer is then removed. The resultant silicon oxide-aluminum surface is planar and undamaged by the chemical-mechanical polishing step.

Abstract: Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.

Abstract: A method in a plasma processing chamber for etching through a selected portion of a layer stack. The layer stack comprises a metallization layer, a first barrier layer disposed adjacent to the metallization layer, and a photoresist layer disposed above the metallization layer. The method includes etching at least partially through the first barrier layer using a high sputter component etch. The method further includes etching at least partially through the metallization layer using a low sputter component etch. The low sputter component etch has a sputter component lower than a sputter component of the high sputter component etch.

Abstract: A method for generating a floating bitline test mode using digitally controllable bitline equalizers is provided. The method utilizes digitally controlled dummy timing cycles to detect a leaky bitline during the floating bitline test mode. A negative pulsed TEST signal is generated to cause the bitline equalizers to go low and cause the floating bitline state. The implementation of dummy timing cycles eliminates the need for additional external control of internal timings during a bitline test mode. Upon the termination of the dummy timing cycle, the normal read operation continues without interruption.

Abstract: The voltage detection and control circuit includes a voltage detect circuit having an associated switch point greater than a first predetermined voltage, with the voltage detect circuit being responsive to an input voltage greater than the first predetermined voltage for generating an activation signal; and a clamp control circuit, responsive to the activation signal, for clamping an operating voltage to a second predetermined voltage. The second predetermined voltage may be substantially equal to the first predetermined voltage. A spike filter may be included for suppressing spikes in the activation signal. A clamp stage control circuit is provided for suppressing oscillations in the second predetermined voltage. At least one clamp stage, which may include a delay device, provides the operating voltage to a corresponding circuit component as well as reducing current peaks in the corresponding circuit component.

Abstract: The spacing of the bit lines and/or the master bit lines (MBLs) of a memory array is skewed to decrease the charging current required to precharge the bit-lines and or the master bit lines. In one embodiment of the invention, an integrated circuit (IC) includes an array of memory cells arranged in rows and columns, with a pair of bit lines (BLTi and BLCi) per column of memory cells with BLTi carrying the cell data and BLCi its complement. The bit lines are disposed within a first level of the IC and run generally parallel to each other wherein there is a certain capacitance, CINT, between each two paired bit lines (BLTi and BLCi) and a capacitance, CEXT, between the bit lines of adjacent columns. The bit lines are coupled to selected MBLs with the MBLs being paired so that one MBL of a pair (MBLT) carries bit line data and the other MBL of a pair (MBLC) carries the complement of that bit line data.

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection includes monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: An improved integrated circuit interconnection for interconnecting at least two conductive regions within an integrated circuit, and method for producing the same. The interconnection includes a tungsten layer and a barrier layer to provide a low contact resistance within the interconnection and between the conductive regions and the interconnection. The interconnection also includes an aluminum layer for providing a low sheet resistance in the current path between the two conductive regions. Thus the invention combines the advantages of an all tungsten interconnection with those of a tungsten capsuled aluminum interconnection.

Abstract: Disclosed is a repairable semiconductor memory array. The repairable semiconductor memory array includes a main memory array 210. A set of redundant rows 212 and a set of redundant columns 214 for repairing a row element or a column element of the main memory array. A fusebank group 216 that is electrically wired to the set of redundant rows and the set of redundant columns. The repairable semiconductor memory array further includes a plurality of fusebanks 218 contained within the fusebank group. Each of the plurality of fusebanks are programmable to address the column element or the row element of the main memory array, and the addressed column element or row element being replaced with one of the set of redundant rows or one of the set of redundant columns.

Abstract: A memory array having a first plurality of fuse-sharing redundant elements for replacing defective elements of the memory array. The memory array includes a first fuse, and first group of redundant elements of the first plurality of fuse-sharing redundant elements. The first group of redundant elements share the first fuse as their highest order address fuse. The memory array further includes a second group of redundant elements of the first plurality of fuse-sharing redundant elements. The second group of redundant elements is mutually exclusive with respect to the first group of redundant elements.

Abstract: The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

Abstract: A programmable fuse element disposed between integrated circuit elements that may be selectively joined during the manufacture or programming of an integrated circuit. The fuse element is a normally open fuse that electrically isolates the integrated circuit elements. The fuse element is comprised of a central area of conductive material insulated from the integrated circuit elements by areas of dielectric material. The integrated circuit elements and the fuse element are disposed on a thin oxide layer covering a semiconductor substrate to prevent those elements from shorting to the semiconductor substrate or to each other via the semiconductor substrate. A protective dielectric layer may be deposited over both the fuse element and the integrated circuit elements during the manufacture of the overall integrated circuit. A laser beam is used to burn through the protective layer and melts both the conductive material and the dielectric material that form the fuse element.