Abstract: Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL.sub.1, LBL.sub.2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense amplifier (SA.sub.i). Local bit lines disposed in any given column are coupled to different numbers of memory cells, i.e., the local bit lines have different lengths (L1, L2) over the memory cells. A hybrid configuration is preferably employed in which one local bit line (LBL.sub.1) in a column is directly coupled via a switch (25.sub.1) to an associated sense amplifier, whereas the other local bit lines in the column (LBL.sub.2 -LBL.sub.4) are operatively coupled to the sense amplifier via the master bit line.

Abstract: A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region.

Abstract: A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

Abstract: Disclosed are metal fuse structures and methods for making the same. The method includes forming the fuse structure from a metallization layer. Depositing a bottom oxide layer, that is an HDP oxide, over the fuse structure that is formed from the metallization layer. Depositing a doped oxide layer over the base oxide layer. Depositing a top oxide layer over the doped oxide layer. Etching through the top oxide layer. Detecting an increased level of a dopant species that is emitted when the doped oxide layer begins to etch. The method further includes terminating the etching when the increased level of dopant species is detected. Wherein at least the bottom oxide layer remains over the fuse structure that is formed from the metallization layer.

Abstract: A process for monitoring and determining the end point of a wet etch process for removing a thin solid film 116 from a substrate by directing a light beam onto the substrate and monitoring the intensity of reflected beams, including the step of selecting a coherence length of the incoming beam 120 so that it is small enough so that no interference occurs in the liquid layer and large enough so that interference can occur in the thin solid film, i.e., light reflected from the interface between the liquid 118 and the top of the thin film, and light reflected from the interface between the bottom of the thin solid film and the substrate interferes. If the liquid layer is about 100 micrometers thick, and the thin film is about 1 micrometer thick, a coherence length of about 10 micrometers is suitable. Such coherence length can be provided with a suitable bandpass filter.

Abstract: A trench capacitor with an epi layer in the lower portion of the trench. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the lower portion of the trench to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

Abstract: Power-on detection circuitry with almost instantaneous response to a power-off condition includes a network of several transistors (30, 32, 38, 40) and a resistor (34). When a supply voltage (+VCC) used with the circuitry is first turned on, the network produces at an output (terminal 52) a short pulse which is subsequently used to generate a power-on (PWRON) signal (line 24) to reset or initialize circuit elements termed "latches" (14). The latches (14) in turn provide operating information to other (main) circuits (16). A reverse coupled diode-connected transistor (30) is provided to shunt to ground charge stored in parasitic capacitance (36) at an input (terminal 50) when power is interrupted, such as by a sudden negative voltage transient. This shunting action of the diode-connected transistor (30) virtually instantly brings the voltage at the input down almost to zero so that whenever power comes back on another short pulse at the output is sure to be generated.

Abstract: An output driver circuit having an output coupled to a resistive termination load comprises: a dual gate pFET device including source and drain transistors, each transistor respectively having a gate, source, and drain, the source transistor source coupled to a voltage source V, the source transistor drain coupled to the drain transistor source, the drain transistor drain coupled to the output of the driver circuit; a dual gate nFET device including source and drain transistors, each transistor respectively having a gate, source and drain, the source transistor source coupled to a ground potential, the source transistor drain coupled to the drain transistor source, the drain transistor drain coupled to the output of the driver circuit; first and second switches, coupled to the source transistor gate of the pFET device and the nFET device, respectively, for turning on and off current flow from the voltage source V through the source transistor of the pFET device and to the ground potential through the source t

Abstract: Apparatus and method are provided for obtaining improved measurement and control of the temperature of a semiconductor wafer (W) during processing. The apparatus includes a chuck for holding a wafer during processing, a coolant gas supply (16), and a temperature sensing arrangement for measuring and controlling the temperature of the wafer during processing. A top face of the chuck (22) over which the wafer is positioned, is configured with a plurality of holes (34) into which the coolant gas, such as helium, is admitted at controlled rate and pressure. The coolant gas passes through a narrow space (36) between the top face of the chuck and the underside of the wafer and is evacuated via an exhaust line (30) after being heated to (or nearly to) the temperature of the wafer. Temperature of the now-heated coolant gas is continuously measured by a temperature sensor arrangement which generates a signal controlling the pressure and flow of coolant gas to the wafer.

Abstract: A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photoresist plug to a level below the depth of a channel also incorporated with the device. A nitride liner disposed within the trench under the photoresist plug is then recessed to a level substantially equal to the level of the photoresist material, which is then removed. The method further includes the deposition of oxide fill within the trench, thereby encapsulating the recessed nitride liner.

Abstract: A memory cell for a dynamic random access memory includes a pass transistor and a storage capacitor. The transistor is a vertical transistor formed along an upper portion of a sidewall of a polysilicon-filled trench in a monocrystalline silicon body with the source and drain in the body and the source contact, gate and gate contact in the trench, with its gate dielectric being an oxide layer on the sidewall portion of the trench. The capacitor is a vertical capacitor formed along a deeper portion of the trench and has as its storage plate a lower polysilicon layer in the trench and as its reference plate a deep doped well in the body. The source contact and the storage plate are in electrical contact in the trench and the source contact and the gate contact are in the trench electrically isolated from one another.

Abstract: A method for forming a Self Aligned Contact in a semiconductor device includes incorporating carbon into a nitride layer during or following the formation of the nitride layer on a semiconductor substrate.

Abstract: Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

Abstract: A complementary metal oxide (CMOS) integrated circuit configured for reducing the formation of silicon defects in its silicon substrate during manufacture. The silicon defects are formed from silicon interstitials present in the silicon substrate. The CMOS integrated circuit includes a deep implantation region formed within the silicon substrate. There is further included at least one vertical trench formed in the silicon substrate. The trench is formed such that at least a portion of the trench penetrates into the deep implantation region of the silicon substrate to present vertical surfaces within the deep implantation region, thereby allowing the silicon interstitials to recombine at the vertical surfaces.

Abstract: In memory systems embodying the invention a controller/sequencer circuit converts a multiplicity of control signals into a serial stream of control signals which are carried from the controller/sequencer circuit via a single ("data") line to the data input of a control path (e.g., a multi-stage shift register) which is disposed in proximity to a functions generator (e.g., a voltages generator). After the control path is serially loaded with a selected number of control signals, the control signals are selectively applied, in parallel, to the functions generator. Where the control path is a shift register, three control lines are routed from the controller/sequencer to the shift register. One line carries the serial control signals to the input of the shift register; one line (i.e., a shift line) carries shift signals for causing the transfer of the control signals along the shift register stages; and one line (i.e.

Abstract: Feedback pulse generators each have an input and an output, a first digital gating circuit, and a second digital gating circuit. The first digital gating circuit is coupled between the input and the output of the pulse generator, and is responsive to an input signal from an external source changing from a first logic state to a second logic state that is received at a first input thereof for initiating a pulse at the output of the pulse generator.

Abstract: Fabrication of devices that produces a surface with reduced dishing caused by polishing. The reduced dishing is the result of forming a first layer that partially covers a complex surface topography and a second layer the covers the surface topography. The second layer being more resistant to polishing than the first so as to reduce dishing in the wide spaces of the complex topography.

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material.

Abstract: Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL.sub.1 -GCSL.sub.(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.

Abstract: Disclosed is a semiconductor memory employing a hierarchical bitline architecture which allows for a widened master bitline pitch as well as low bitline capacitance. In an exemplary embodiment, the memory (30) includes a plurality of memory cells (MC) arranged in rows and columns for storing data. Each column has at least one sense amplifier (SA.sub.i), at least one pair of master bitlines (MBL.sub.i, MBL.sub.i ) operatively coupled to the sense amplifier, and at least two pairs of local bitlines (LBL.sub.1i, LBL.sub.1i , LBL.sub.2i, LBL.sub.2i ), coupled to memory cells and selectively coupled to the sense amplifier. At least one of the local bitline pairs is selectively coupled to the sense amplifier via the master bitline pair. Each master bitline pair has a length shorter than a column length, and the master bitlines are arranged in an interleaved configuration. The pitch of at least a portion of at least some of the master bitlines is greater than the local bitline pitch.