Abstract: An integrated circuit has a matrix of memory cells with a capacitive element and an access transistor. A plate conductor is connected to terminals of the capacitive element of all the memory cells. A voltage boost circuit boosts a voltage of the plate conductor to a voltage level outside a power supply range of the integrated circuit. A switching element is connected between the plate conductor and a control electrode of the access transistor. Thus the access transistor is controlled with the voltage of the plate conductor. Preferably, the voltage of the plate conductor is boosted below Vss and at a level regulated relative to Vdd.
Type:
Grant
Filed:
May 24, 1999
Date of Patent:
April 17, 2001
Assignee:
U.S. Philips Corporation
Inventors:
Johannes A. J. Van Geloven, Cornelis G. L. M. Van Der Sanden
Abstract: An optical read/write apparatus includes a first detector for detecting light reflected from an optical record carrier and generating a signal; and a signal processing unit. The processing unit includes: a common input clamp coupled to the first detector; separation apparatus for separating low frequency and high frequency components of the detected signal, including a capacitive element; low frequency apparatus for processing the low frequency components and including a current mirror having a first output clamp and a first input clamp coupled to the common input clamp. The processor unit further includes high frequency apparatus for processing the high frequency components and including: a current source with a current output clamp; a second current mirror with an input branch; a second input clamp coupled to the common input clamp via the capacitive element; and a second output clamp.
Abstract: A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For reducing the communication rate of the digital output signal a time frame of subsampling periods is created and, within each subsampling period, the position of samples, which approximately coincide with the transients of the square wave, is determined. The invention further provides an image sensor comprising a plurality of such arrangements.
Abstract: Element comprising a substrate (101) having a layer structure (103) bounded by two parallel main faces (105a, 105b) with at least two layers of mutually different magnetical behavior. The layer structure has a zone (109) which, viewed in a direction parallel to the main faces, extends between spaced electric connection areas (107a, 107b). A current-directing means is present in this zone for producing, during current passage, a current component (cp) directed transversely to the layer structure, which means comprises at least one electric conductor (111a, 111b) on at least one of the main faces.
Abstract: An integrated circuit provided with ESD protection means comprising a silicon-controlled rectifier whose n-well (WLL), if the substrate (SBSTR) of the integrated circuit is of the p-type, is connected to the VDD supply instead of to the bonding-pad (BP) to which electronic circuitry is connected. Consequently, the anode is only formed by the p+ diffusion (d4) in the n-well (WLL). Therefore, negative voltages are allowed at the bonding pad (BP) because the junction is not forward-biased. Thus, an ESD protection towards the VSS is obtained. Additionally, a PMOST (MP) is used as an ESD protection towards the VDD.
Abstract: An arrangement for controlling at least one predetermined function, which can be transmitted from at least one transmission apparatus (1) to a receiving apparatus (11) via a serial data bus, is protected against unintentional triggering of the predetermined function in that in order to control a predetermined function the transmission apparatus (1) dispatches an associated, predetermined data message on the serial data bus (7) and adjusts a transmission parameter of the data bus to a predetermined value, and in that the receiving apparatus (11) triggers the predetermined function only if the predetermined data message appears on the data bus (7) with the predetermined transmission parameter.
Abstract: The invention relates to an apparatus for processing a signal received via an information carrier. The apparatus comprises a receiving unit (2) for receiving a signal from the information carrier, an equalizer (8) for equalizing the signal thus received, and a signal processing device (12). The signal processing device (12) has a first signal path (14) including time delay means (22), a second signal path including differentiation means adapted to effect at least two differentiations with respect to time, a decision circuit (26), and a controllable switching element (38). The decision circuit (26) is adapted to transfer a control signal, the decision circuit being adapted to supply a control signal which depends upon the signals on the outputs (28, 32) of the first signal path (14) and the second signal path (16).
Abstract: A semiconductor device, for example an IC, having conductor tracks (3) of a metal (3) exhibiting a better conductance than aluminium, such as copper, silver, gold or an alloy thereof. The tracks are situated on an insulating layer (2) and are connected to a semiconductor region (1A) or to an aluminium conductor track by means of a metal plug (5), for example of tungsten, which is situated in an aperture (4) in the insulating layer (2). The bottom and walls of the aperture (4) are provided with an electroconductive material (6), such as titanium nitride, which forms a diffusion barrier for the metal (3). In accordance with the invention, the insulating layer (2) comprises a sub-layer (2A), which forms a diffusion barrier for the metal (3) and which extends, outside the aperture (4), throughout the surface of the semiconductor body (10). As a result, the conductor tracks (3) no longer have to be provided with a sheath serving as a diffusion barrier for the metal (3).
Type:
Grant
Filed:
December 10, 1998
Date of Patent:
March 13, 2001
Assignee:
U.S. Philips Corporation
Inventors:
Srdjan Kordic, Cornelis A. H. A. Mutsaers, Mareike K. Klee, Wilhelm A. Groen
Abstract: A semiconductor device comprising a silicon substrate is provided with semiconductor elements on a first side, a metallization with connection pads for external contact, and a passivation layer which leaves the connection pads of the metallization exposed. The integrated circuit thus formed is also provided with a ceramic security coating having a matrix of monoaluminium phosphate which also leaves the connection pads of the metallization exposed. The protective layer can be deposited so as to have a thickness in the range from 2 to 10 &mgr;m, and hence is suitable for protecting integrated circuits used in smart cards. As a result, the information stored therein is not accessible.
Type:
Grant
Filed:
June 8, 1999
Date of Patent:
March 6, 2001
Assignee:
U.S. Philips Corporation
Inventors:
Nijnke A. M. Verhaegh, Joseph G. Van Lierop, Marcus J. Van Bommel
Abstract: A converter for converting an input voltage (Ui) into an output voltage (U0). The converter has several modes of operation. The converter can, for example, operate in an up-conversion mode, a down-conversion mode, or a window conversion mode. The converter has at least one switch (S1-S4) for controlling the converter so as to obtain a desired value of the output voltage (U0) in the up-conversion mode and in the down-conversion mode. This is achieved by changing the duty cycle of a binary signal (BS) which controls the switch (S1-S4). The converter further includes means (DMNS) for detecting the duty cycle of the binary signal (BS). This duty cycle is compared with a reference duty cycle (RFDCCL). The result of this comparison is used for deciding whether or not to change over from the up-conversion mode (or the down-conversion mode) to the window conversion mode. In the window conversion mode each switch (S1-S4) in the converter is permanently closed or open.
Abstract: A switched-mode power supply with a burst mode comprises an integrated circuit (Ic) with a minimal number of terminals. The integrated circuit (Ic) comprises a switching element (S) for periodically switching on and off the current (Id) in a primary winding (Lp) of a transformer (T), and a control circuit (Cc) for controlling the on and off-switching of the switching element (S). The integrated circuit (Ic) has three terminals (T1, T2, T3). A main current path of the switching element (S) is arranged between two of the terminals (T1, T2). A capacitor (C1) is connected to the third terminal (T3). A capacitor voltage (Vc) across the capacitor (C1) is used as power supply voltage for the control circuit (Cc). A feedback circuit (Fb) has an input connected to a DC output voltage (Vout) supplied by a secondary winding (Ls) of the transformer (T), and an output connected to the third terminal (T3).
Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a Lateral Insulated Gate Bipolar Transistor (LIGBT) device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first and a body contact region of the second conductivity type in the body region and connected to the source region. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region with an anode region of the second conductivity type in the drain region and connected to the drain contact region.
Type:
Grant
Filed:
December 13, 1999
Date of Patent:
February 20, 2001
Assignee:
Philips Electronics North America Corporation
Inventors:
John Petruzzello, Theodore Letavic, J. Van Zwol
Abstract: The invention relates to a positioning device with an X-beam (6) and two parallel Y-beams (2,3) in the shape of an H. On each Y-beam a motor driven carriage (4,5) is provided. Between these carriages an X-beam is coupled. On the X-beam a carriage (9) with a positioning head (10) is provided. The coupling (7) between one end of the X-beam and the carriage (4) on the first Y-beam (2) comprises two leaf springs (19,20) perpendicular to each other, the intersecting line of said leaf springs forming an imaginary rotation axis (28) of the coupling. The coupling (8) between the other end of the X-beam and the carriage (5) on the other, second Y-beam (3) comprises one leaf spring (29) oriented in the Y-direction and having a relatively great stiffness in the Y-direction and a relative small stiffness in the X-direction. Advantage of these couplings: no play, frictionless, possibility of small angle correction for the positioning head.
Abstract: Methods and arrangements are provided for a block decoder in the form of a single integrated circuit (IC) for use in a variety of data storage devices. The block decoder is configured to transfer streaming data from the storage medium to an external device, such as a host computer's processor, without introducing any significant overhead induced latency into the data transfer. This is accomplished by employing a purely hardware-based logic and substantially minimizing the amount of buffering of data that is required within the storage device. The resulting block decoder can be integrated into a single IC because the amount of buffering memory that is required can be economically fabricated using conventional logic fabrication processes, such as complementary metal oxide semiconductor (CMOS) processes.
Type:
Grant
Filed:
June 19, 1998
Date of Patent:
February 6, 2001
Assignee:
Philips Electronics North America Corporation
Abstract: A current amplifier A1 includes two transistors Q1 and Q2 whose emitters are interconnected via a resistor R1. The input of the current amplifier is constituted by the emitter of the first transistor Q1, whose collector is connected to the output terminal of the amplifier A1 via a second resistor R2, and to the first resistor R1 via the main current path of the second transistor Q2. The current amplifier A1 has a simple structure and a low input impedance, as well as an easily controllable gain.
Abstract: Known salicide processes have the disadvantage that they may cause a short circuit between silicide contacts on source and drain regions, on the one hand, and the silicide contact on the poly gate, on the other hand, which is commonly referred to as bridging. The invention provides a simple and self-aligned method of avoiding this type of short-circuit. After the gate definition, a titled source/drain implantation (9) is carried out, while the resist mask (7) is held in place, the angle and the implantation energy being chosen such that ions impinging on the resist mask are scattered at a small angle with respect to the silicon surface. Apart from the gate, small areas (12b, 13b) are obtained thereby, which are more heavily doped than adjacent areas (12a, 13a) of the source/drain regions. Subsequently, a thermal oxide layer is grown having thicker portions (15) on top of the more heavily doped regions, and thinner portions (14) on top of the more lightly doped regions.
Type:
Grant
Filed:
April 27, 2000
Date of Patent:
January 23, 2001
Assignee:
U.S. Philips Corporation
Inventors:
Hendrik H. Van Der Meer, Klaas G. Druijf, Adrianus C. L. Heessels
Abstract: To improve the efficiency of UV erasing in a non-volatile memory, there is proposed to carry out the erase step at an elevated temperature, for example, a temperature lying between 200 and 300° C. In this way a decrease of about 0.5 volt of the threshold voltage of the erased cell may be obtained compared to a standard UV erasure. This makes it also possible to lower the supply voltage.
Abstract: In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).
Type:
Grant
Filed:
August 24, 1999
Date of Patent:
January 23, 2001
Assignee:
U.S. Philips Corporation
Inventors:
Jurriaan Schmitz, Pierre H. Woerlee, Andreas H. Montree
Abstract: A method of manufacturing enveloped semiconductor devices, in which use is made of a slice of a semiconductor material which is provided on its first side with an intermediate layer of an insulating material on which a top layer of a semiconductor material is formed, semiconductor elements are formed in the top layer, paths of the slice's surface situated on this side being left clear between the semiconductor elements, and the top layer is removed from the insulating intermediate layer at the location of the free paths. A metallization with connection electrodes extending as far as the free paths are formed on the first side of the slice, the slice is glued with its first side onto a transparent insulating supporting body, semiconductor material is removed from the second side of the slice facing away from the first side, and the slice thus reduced in thickness is provided on its second side with a layer of an insulating material.
Abstract: A thin film semiconductor device includes a glass supporting body having thereon an insulating substrate which is attached thereto by a layer of adhesive material. On the surface of the substrate facing the supporting body is a layer of semiconductor material which includes therein a semiconductor element, such surface further having thereon a metalization pattern of conductor tracks. An insulating layer is additionally provided between the metalization pattern and the adhesive layer, and has a dielectric constant &egr;r below 3 and a thickness in the range of approximately 20 &mgr;m to 60 &mgr;m. By virtue of such additional layer, parasitic capacitanees between the metalization pattern and an envelope in which the device is included or a printed circuit board on which the device is mounted are reduced substantially, thereby reducing the power consumption of the device.
Type:
Grant
Filed:
February 26, 1999
Date of Patent:
January 23, 2001
Assignee:
U.S. Philips Corporation
Inventors:
Ronald Dekker, Henricus G. R. Maas, Maria H. W. A. Van Deurzen