Abstract: A DC/DC up/down converter (10), comprising first and second input terminals (20, 21); first and second output terminal (30, 31); a coil (L); first switching means (S1) operatively connected to provide a conduction path from said first input terminal (20) to said coil (L) second switching means (S2) operatively connected to provide a conduction path from said first switching means (S1) and said coil (L) to said second input terminal (21); third switching means (S3) operatively connected to provide a conduction path from said coil (L) to said first output terminal (30); fourth switching means (S4) operatively connected to provide a conduction path from said coil (L) and said third switching means (S3) to said second output terminal (31); control means (11) operatively connected for controlling said switching means (S1, S2, S3, S4); reference voltage means (12) for providing a reference voltage (Vr); and comparator means (13) for providing a comparison signal (Vc) for said control means (11) in response to compa

Abstract: The invention relates to a bipolar ESD protection comprising a protection transistor with a short-circuited base emitter (18, 19). Due to the snap-back effect, the transistor can switch from the normal high-ohmic condition to a low-ohmic condition in the case of ESD. To improve the protection performance, the protection structure is provided with a trigger element comprising a second transistor (26, 27, 28) with a lower breakdown voltage. The base (26) and the emitter (28) of the second transistor are connected to the base of the protection transistor. To increase the current carrying capability of the protection device, the trigger transistor is designed so as to be a vertical transistor.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region.

Abstract: Resonator comprising first and second balanced integrators (I1, I2) each composed with a balanced amplifier and having a non-inverting (in+) and an inverting (in−) input terminal, as well as a non-inverting (out+) and an inverting (out−) output terminal. First and second coupling circuits (Y1, Y2) are interconnected between the non-inverting output terminal (out+) of the first integrator (I1) and the non-inverting input terminal (in+) of the second integrator (I2) and between the inverting output terminal (out−) of the first integrator (I1) and the inverting input terminal (in-) of the second integrator (I2) respectively.

Abstract: The invention relates to a method of manufacturing an assembly (100) of conductors (1), wherein a void (11) is provided in an electroconductive plate (10), within which void an island (12) is formed which serves as a carrier for a semiconductor element (13) and which is connected to the assembly (100) by a part (14) of the plate (10). Within the void (11), a number of strip-shaped conductors (1) are formed which surround the island (12), and the void (11) is formed so that one (1n) of the strip-shaped conductors (1) is connected to the island (12) by means of a further part (15) of the plate (10). Such a method has the drawback that it is not capable of providing an assembly (100) which can suitably be used for any semiconductor element (13). In particular, said method is expensive for ICs (13) which must demonstrate an electrical connection to the island (12) and which must be supplied in relatively small numbers.

Abstract: A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

Abstract: A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell. The output node of each inverter is selectively connected via the conductor paths of separate access transistors to respective bit lines. The control electrodes of the access transistors are connected to a common word line. In particular, both RAM and programmable Read-Only operation of said memory cell are provided. Thereto, the cross-coupling comprises capacitors (C1, C2) each in series with a control electrode of a respective p-type transistor of the first and second inverters. This renders both interconnecting nodes between a capacitor and the gate electrode of its associated p-channel transistor floating. Isolators around these nodes render the cell data-retentive. The nodes are transiently and electrically programmable through signals on the bit and word lines of the cell.

Abstract: Aberrations of an imaging system (PL) can be detected in an accurate and reliable way by imaging, by means of the imaging system, a test object having circular phase structure (22) on a photoresist (PR), developing the resis and scanning it with a scanning detection device (SEM) which is coupled to an image processor (IP). The circular phase structure is imaged in a ring structure (25) and each of several possible aberrations, like coma, astigmatism, three-point aberration, etc. causes a specific change in the shape of the inner contour (CI) and the outer contour (CE) of the ring and/or a change in the distance between these contours, so that the aberrations can be detected independently of each other.

Abstract: The invention relates to a holder for a semiconductor substrate including a main body which is provided with three or more projections by means of which the substrate can be held fixed in the holder. Two projections are fixedly connected, and a third projection present opposite the other two is movably connected to the main body. The third projection can be moved away from the other two and is urged towards the latter two by means. According to the invention, a lateral side of each projection facing towards the substrate to be inserted is provided with a convex recess whose geometry is such that exclusively the outermost edges of both the upper surface and the lower surface of the substrate to be inserted come into contact with the convex recess. A substrate, for example a round substrate, can be satisfactorily fastened in such a holder while still its entire surface area can be processed.

Abstract: A data transfer system transfers frames with more than two data words from a transmitter 100 to at least one receiver 102 in a time-multiplexed manner. The transmitter 100 and receiver(s) 102 are connected via four signal lines: a clock signal 112, a serial data signal 110, a word-select signal 114 and a frame-begin signal 116. The data is serially transferred via the serial data line 110, in synchronisation with periodic clock pulses of the clock signal 112. The word-select signal 114 triggers selecting a next transmit channel register from which the transmitter 100 transmits the next data word and a next receive channel register into which the receiver 102 stores the data word to be received next. The frame-begin signal 116 triggers selecting a first one of the channel registers. The data transfer system may, for instance, be used for transferring eight digital audio channels in a DVD player between components such as an input/output interface, a filter, a (de-)coder or a digital signal processor.

Abstract: The common mode component in the difference signal on the bus terminals (2, 4) of a CAN bus is counteracted by four transistors (M1-M4) connected between the supply terminals (28, 32) and a center tap (16) of a voltage divider (6A, 6B, 8, 10, 12A, 12B) between the bus terminals (2, 4). As a result of this, the voltage on the center tap (16) varies to a substantially smaller extent or not at all. Thus, it is possible to use a simpler differential amplifier (20) having a smaller common mode swing at the inputs (22, 24). Moreover, the attenuation factor selected for the voltage divider can be smaller, as a result of which a higher difference voltage is available for the differential amplifier (20).

Abstract: Component placement machine with a frame (1) and a transport device (2) for transporting printed circuit boards (3) in an X-direction, which transport device is provided with a transport belt (9) having an outer surface (13) on which printed circuit boards (3) are positioned. During the transport of printed circuit boards (3) as well as during the placement of components (6) on the printed circuit boards (3) an edge portion (12) of the printed circuit board which extends in the X-direction is retained between the outer surface (13) of the transport belt (9) and a contact surface (11) of the frame (1). The outer surface (13) of the transport belt has a relatively high coefficient of friction in contact with said edge portion (12) of the printed circuit board, whereas said contact surface (11) of the frame has a relatively low coefficient of friction in contact with said edge portion (12) of the printed circuit board.

Abstract: An object (14) is imaged on an imaging surface (16) by means of a telescopic system of rotationally symmetrical electron lenses (10, 12). The imaging system includes two quadrupoles, each of which coincides with one of the two round lenses (10, 12), so that the electrons are concentrated in line-shaped focal spots instead of a (small) circular cross-over (18). The system remains telescopic to a high degree and the imaging remains stigmatic.

Abstract: An electronic apparatus comprising a fingerprint sensing device (10) having an array of sensing elements (12) carried on a transparent substrate (35) for sensing capacitively the ridge pattern of a fingerprint placed over the array, in which the transparency of the device is utilised to provide additional capabilities. Thus, an optical sensing device (60) may be disposed beneath the device (10) to sense optically through the device a further biometric characteristic, or the presence, of the finger overlying the sensing element array. Substantial transparency can be afforded to the device by forming the sense electrodes (30) of the array from transparent conductive material. In products like mobile telephones, notebook computers, PDAs, smart cards or like portable electronic products of small size such as fingerprint sensing device can then advantageously be arranged overlying a display device with the display output being visible through the device.

Abstract: A lateral metal-oxide-semiconductor field effect transistor (LMOSFET) having a self-aligned gate, includes a first layer of SiC semiconductor material having a p-type conductivity, and a second layer of SiC semiconductor material having an n-type conductivity formed on the first layer. Source and drain regions having n-type conductivities are formed in the second SiC semiconductor layer. The n-type conductivities of the source and drain regions are greater than the n-type conductivity of the second SiC layer. A trench extends through the second SiC semiconductor layer and partially into the first SiC semiconductor layer. The trench is coated with a layer of an electrically insulating oxide material and partially filled with a layer of metallic material. The layers of oxide and metallic material form a gate structure.

Abstract: A semiconductor device (1) with an operating frequency above 50 MHz comprises a body (2) composed of a soft ferrite material, which body (2) has a surface (3) to which a semiconductor element (4), a pattern of conductors (5,6) and a passive element in the form of a planar inductor (7) are fastened by means of a layer (8) of adhesive. In order to reduce the manufacturing costs of the semiconductor device without adversely affecting the performance of the semiconductor device performance, a soft ferrite material is applied having a ferromagnetic resonance frequency smaller than the operating frequency of the semiconductor device.

Abstract: An arrangement (1) for converting voltage (Vin) into current (Iout), implemented on a chip (100), comprises a first V/I converter (3), the operation of which is based on a conversion resistor (Rconv) formed on the chip. This resistor has an unknown fabrication tolerance (&agr;). This is compensated for by the presence of a second V/I converter (13) having a compensation resistor (Rcomp), which is also formed on the chip and which has the same fabrication tolerance (&agr;). Furthermore, a third V/I converter (23) is present, which operates on the basis of an external resistor (Rref). The second V/I converter (13) converts a reference voltage (Vref) into a compensation current signal (Icomp), and the third V/I converter (23) converts the reference voltage (Vref) into a reference current signal (Iref).

Abstract: The present invention relates to an input buffer for a switched emitter follower-like track-and-hold amplifier comprising an input stage with an input transistor (Q1), a first diode (Q2, Q2b), a cathode side of which first diode (Q2, Q2b) is connected to an emitter of the input transistor (Q1), a first current source (4) between on the one hand the junction between the cathode of the first diode (Q2, Q2b) and the emitter of the input transistor (Q1) and on the other hand a first supply voltage line (2), an anode of the first diode (Q2, Q2b) being connected to a track-and-hold controlled emitter follower (6). The first current source (4) is a non-switched constant current source, and a second current source (M1) is connected between a collector of the input transistor (Q1) and a second supply voltage (3).

Abstract: A trench gate field effect device has a semiconductor body (2) with a trench (3) extending into a first major surface (2a) so as to define a regular array of polygonal source cells (4). Each source cell contains a source region (5a,5b) and a body region (6a,6b) with the body regions separating the source regions from a common further region (20). A gate (G) extends within and along said trench (3) for controlling a conduction channel through each of the body regions. Each source cell (4) has a central semiconductor region (60) which is more highly doped than said body regions, is of opposite conductivity type to the further region and forms a diode with the further region. Each source cell (4) has an inner trench boundary (3a) and an outer polygonal trench boundary (3b) with the inner trench boundary bounding a central subsidiary cell (10a) containing the central semiconductor region (60).

Abstract: A high-voltage level tolerant transistor circuit, comprising a plurality of cascoded transistors, including a first transistor (T1) operatively connected to a high-voltage level node (3) and a second transistor (T2) operatively connected to a low-voltage level node (2). The first transistor (T1) connects to a biasing circuit (8), such as a voltage level shifter, providing a variable biasing level (V1) relative to a voltage level (VH) at the high-voltage level node (3).