Abstract: An in-motion measuring system for determining the length and width of linearly-moving cuboidal objects through the use of object speed, the times during which six light beams oriented across the path of the object are obstructed by the object, and the angles of the light beams with respect to the direction of object movement. The height of an object may also be determined through use of a vertically-extending light curtain with horizontally-oriented light beams, or via an ultrasonic sensor.
Abstract: An apparatus and method of forming improved wire bonds between the contact pads on semiconductor devices and individual lead frame fingers of a lead frame. The apparatus and method includes the use of a penetrating individual independent lead finger clamp during the wire bonding process to provide increased stability of the individual lead finger for improved bonding by the clamp penetrating a portion of the lead finger being bonded. If desired, the apparatus and method also provides for the use of either a penetrating or non-penetrating fixed clamp for the lead fingers during the wire bonding process in addition to the penetrating individual independent lead finger clamp during the wire bonding process to provide increased stability of the individual lead finger for improved bonding.
Abstract: A fishing lure has a battery-powered oscillator circuit positioned within a water-resistant container module that is removably inserted into a selected body module that is balanced to insure proper lure action even as fish-attracting sounds and motions are generated from the container module.
Abstract: An inventive method tracks IC devices through the assembly steps in a manufacturing process. Prior to die attach, a laser scribe marks the lead frame of each of the devices with a coded hole matrix that gives each device a unique ID code. During die attach, an optical hole reader retrieves the ID code of each of the IC devices, and a computer system stores the retrieved ID codes in association with the lot numbers of the ICs attached to the lead frames. The ID codes of the devices are then read at each step in assembly so the devices can be tracked through assembly individually, rather than by lots. As a result, the devices can proceed through assembly in a more efficient, continuous manner (i.e., without breaks between lots).
Abstract: An integrated circuit is provided having an alignment feature integral with the lead frame. The integrated circuit includes a lead frame coupled with a semiconductor die, and is partially encapsulated in insulating material. The lead frame has the alignment feature therein. The alignment feature includes a cut out on the lead frame taking the form of a semi-circle, protuberance, apertures, or slots. Alternatively, the alignment feature includes a removably coupled tab. After testing of the integrated circuit has been completed, the alignment tab is removed from the integrated circuit. The alignment feature can also be provided on a heat spreader which is attached to a side of or within the lead frame package.
Type:
Grant
Filed:
September 15, 1997
Date of Patent:
April 11, 2000
Assignee:
Micron Technology, Inc.
Inventors:
David J. Corisis, Tracy Reynolds, Michael Slaughter, Daniel Cram, Leland R. Nevill, Jerrold L. King
Abstract: An apparatus for stabilizing a semiconductor die and lead fingers of a lead frame during the process of wire bonding comprising a rigid clamp having at least one bond site window extending therethrough and at least one resilient secondary clamp which extends from an edge of the bond site window to a position over and in contact with lead fingers extending over the semiconductor die. The arrangement of the secondary clamp is such that the contact force with the semiconductor die is sufficient to minimize, dampen, or prevent movement of the semiconductor die and/or lead finger bounce during the wire bonding process. Methods of clamping are also disclosed.
Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
Abstract: An improved process for making asphalt involves incorporating tar sands into a hot asphalt mix process and modifying the process. The improved process involves using a heated asphalt counter-flow drum mixer to admix asphaltic cement, coarse aggregate, and fine aggregate. During this mixing process, the admixture is heated to produce the asphaltic concrete. In the improved process from about 20 to about 80 percent tar sand is mixed with from about 80 to about 20 percent aggregate and from about 1 to less than about 5 percent liquid asphalt cement in a drum mixer to form an admixture, heating the admixture to a first elevated temperature (e.g., 250.degree. and 400.degree. F.) for a set period of time (e.g., 40 to about 90 seconds); and discharging the heated admixture at a second elevated temperature (e.g., from about 150.degree. to about 350.degree. F.) to produce asphaltic concrete.
Abstract: A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
Type:
Grant
Filed:
February 23, 1998
Date of Patent:
April 4, 2000
Assignee:
Micron Technology, Inc.
Inventors:
David R. Hembree, Michael E. Hess, John O. Jacobson, Warren M. Farnworth, Alan G. Wood
Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store "1" and "0" bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each "1" or "0" bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each "1" and "0" bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.
Abstract: A packaging technique for high speed components, such as high speed DRAMS, may involve a package which includes two opposed edges, one edge adapted to receive a power supply and ground contacts which may be ganged together to form a ganged power supply lead and a ganged ground lead. A second edge is arranged to receive normal signal contacts. In this way, the lead inductance may be minimized and the operation efficiency of the package may be improved.
Abstract: A method of non-invasively estimating the intrapulmonary shunt in a patient. The method includes non-invasively measuring respiratory flow, respiratory carbon dioxide content, and arterial blood oxygen content. A re-breathing process is employed to facilitate an estimate of the patient's pulmonary capillary blood flow. Any inaccuracies of the arterial blood oxygen content are corrected to provide a substantially accurate arterial blood oxygen content measurement. The respiratory flow and carbon dioxide content and arterial blood oxygen content measurements, and the pulmonary capillary blood flow estimate are employed to estimate an intrapulmonary shunt of the patient. The invention also includes a method of determining the total cardiac output of the patient which considers the estimated intrapulmonary shunt.
Type:
Grant
Filed:
September 9, 1998
Date of Patent:
March 28, 2000
Assignee:
NTC Technology, Inc.
Inventors:
Dinesh G. Haryadi, Joseph A. Orr, Kai Kuck, Michael B. Jaffe
Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6 F.sup.2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.
Abstract: After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etch process forms the bit line contact region through the cell poly, then a thin oxide is deposited and etched along with the oxide 1 to form cell poly spacers that don't close off the active area. The poly or nitride on top of the oxide 2 forms a hard mask that allows the spacers to travel down the side walls of the contact region creating a contact region that is wider at the top than bottom, facilitating metalization.