Abstract: A semiconductor device includes a first wall and a second wall. The first wall is arranged in a pad region which surrounds a chip region, and the second wall is arranged on a semiconductor chip mounted in the chip region. Conductive are arranged between the first wall and the second wall and are encapsulated by a encapsulating material formed between the first and second walls.

Abstract: A split-gate semiconductor device is fabricated by forming floating gates on the sidewalls of the control gates of transistors, then using a bottom anti-reflective coating as a mask while removing unnecessary floating gates, preferably by an isotropic dry etching process that removes floating-gate material from the sidewalls faster than it removes dielectric material from the upper parts of the control gates. Alternatively, control gate structures are formed, floating-gate material is deposited, removed, then deposited again to form floating gates on the sidewalls of the control gate structures, and the central parts of the control gate structures are etched to leave control gates with floating gates on one sidewall each.

Abstract: An electrostatic discharge (ESD) protection circuit includes an MOS transistor acting as a trigger for the circuit. A drain region of the MOS transistor is formed by an N-type heavily doped impurity region which overlaps an N-type well region. Further, a P-type heavily doped impurity region is formed in the N-type well region. The N-type and P-type heavily doped impurity regions are electrically connected to an input/output pad. The ESD protection circuit exhibits a reduced input capacitance at the pad, and a reduced breakdown voltage of the MOS transistor.

Abstract: A method of manufacturing a semiconductor device, according to the present invention comprises a step for forming an insulating film over a semiconductor wafer and thereafter subjecting the same to photolithography and etching to thereby define a contact hole, a step for forming an adhesive layer over the insulating film with the contact hole defined therein, a step for placing the interior of a processing chamber under an atmosphere uncontaining oxygen and subjecting the adhesive layer to heat treatment, a step for setting the temperature of the semiconductor wafer to less than or equal to a temperature equivalent to energy of such an extent as to cut the bonding between atoms which form the adhesive layer and thereafter taking the semiconductor wafer out of the processing chamber, and a step for forming an embedding film to be embedded in the contact hole.

Abstract: A cleaning apparatus for removing contaminants from the surface of a substrate includes two parts: one which produces an aerosol including frozen particles and directs the aerosol onto the surface of the substrate to remove contaminants from the surface by physical force, and another part in which a fluid including a gaseous reactant is directed onto the surface of the substrate while the surface is irradiated to cause a chemical reaction between the reactant and organic contaminants on the surface, to chemically removing the organic contaminants. In the method of cleaning the substrate, the physical and chemical cleaning processes are carried out in a separate manner from one another so that the frozen particles of the aerosol are not exposed to the effects of the light used in irradiating the surface of the substrate. Therefore, the effectiveness of the aerosol in cleaning the substrate is maximized.

Abstract: An object of the present invention is to provide a method for manufacturing a capacitor structure that makes it possible to control the accumulation of electric charges on a top electrode film as a factor that brings about electrostatic breakdown in the insulating film of an MIM capacitor structure, and to provide a method for manufacturing capacitor elements with a low percent defective. The first technique is characterized in that a top electrode film is formed on a substrate after a grounded conductive member is brought into contact with a bottom electrode film or insulating film, and the conductive member is then separated from the bottom electrode film or insulating film. The second technique is characterized in that a top electrode film is formed on a substrate in a state in which a member kept at a negative potential is disposed around the substrate.

Abstract: An exposure apparatus and an exposure method that minimize the range over which exposing light becomes defocused even when a non-level portion is present within each shot are provided. One shot is selected from a plurality of shots (exposure unit areas) set on a wafer (S 50). 49 measurement points are set in the selected shot and the three-dimensional coordinates of each measurement point are determined (S 70). Next, an arithmetic operation is performed using the 49 sets of three-dimensional coordinate data to ascertain an “in-shot focus plane” (S 90). This arithmetic operation may be performed through, for instance, the method of least squares. The extents of positional deviation between the surface of the selected shot and the in-shot focus plane is ascertained and the extents of deviation are stored in memory as “adjustment values” (S 110). An exposure shot to undergo exposure processing is selected and the surface level variation manifesting at the exposure shot is measured.

Abstract: Two electrodes parallel to each other are formed on one of two substrates, homeotropic alignment films are formed on the substrates and a liquid crystal material having positive dielectric anisotropy is injected between the substrates. When a voltage is applied to the two electrodes, a parabolic electric field between the electrodes drives the liquid crystal molecules. Since the generated electric field is symmetrical with respect to the boundary-plane equal distance from each of the two electrodes, the liquid crystal molecules are symmetrically aligned with respect to the boundary-plane, and the optical characteristic is compensated in both regions divided by the boundary-plane, thereby obtaining a wide viewing angle. The electric field does not exert influences on the liquid crystal molecules on the boundary-plane since the electric field on the boundary-plane is parallel to the substrates and perpendicular to the two electrodes: and thus, it is perpendicular to the liquid crystal molecules.

Abstract: A DRAM cell is provided, along with a method for fabricating such a DRAM cell. A protection layer pattern is formed to cover a common drain region of first and second access transistors. Storage node holes are then formed to expose each source region of the first and second access transistors, by using an etching insulator that has an etching selectivity with respect to the protection layer. Accordingly, even if there is a misalignment of the storage node holes to the source regions, the common drain region is not exposed by the misaligned storage node holes because of the presence of the protection layer pattern.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: An A/D converter includes first to Nth stages of A/D conversion units, which are connected in series, each A/D conversion unit converting an analog input signal into a digital output signal. Each of the A/D conversion units includes a) a sample-and-hold circuit, which holds an analog input signal; b) a selector which selects one from a plurality of reference voltage signals in accordance with a digital output signal outputted from the one stage preceding A/D conversion unit; and c) a comparator which compares an output signal supplied from the sample-and-hold circuit with the reference voltage signal selected by the selector.

Abstract: A semiconductor device including a P-type semiconductor layer; an N-type first well on the surface of the semiconductor layer; a P-type second well on the surface of the first well; an N-type source region on the surface of the second well; and an N-type drain region on the surface of the first well and apart from the source region at a specific distance. A gate electrode is formed on the semiconductor layer and extends from the source region to the second well and the first well. An application electrode is arranged apart from the gate electrode on the first well between the second well and the drain region, and extends from the first well to the edge thereof. A P-type first impurity diffusion layer is formed on the surface of the source region and extends to the second well under the source region.

Abstract: An echo canceler provided with a noise detecting section which holds signals showing a presupposed ambient noise such as a horn of a vehicle. The noise detecting section is adapted to monitor a sending signal received through a microphone and, while detecting such ambient noises in the sending signal, an adaptive filter outputs a pseudo echo existing immediately before the ambient noise is detected. Even during the generation of ambient noises, an echo noise can be eliminated and the generation of a foreign voice (noise) can be avoided as well.

Abstract: A chemical mechanical polishing apparatus includes a polishing pad on which a wafer requiring planarization is placed, a conditioning disc having an abrasive surface for conditioning the polishing pad, a tank containing de-ionized water in which the conditioning disc soaks while standing by, and a cleaner for cleaning the conditioning disc. The conditioning disc cleaner is disposed in the tank of de-ionized water to remove polishing impurities from an abrasive surface of the conditioning disc. The cleaner may include a brush having bristles against which the abrasive surface of the conditioning disc is placed when it is lowered into the tank. In operation, after the wafer is polished, an abrasive surface of the conditioning disc is run over the upper surface of the polishing pad to condition the surface of the polishing pad. Then the conditioning disc is moved off of the upper surface of the polishing pad and to a stand-by position in which the abrasive surface of the disc is submerged in a liquid.

Abstract: The operation of a polishing pad conditioner for a CMP apparatus is monitored. The polishing pad conditioner includes a housing, a first drive pulley disposed in the housing and connected to a motor at a first side of the housing, a conditioning head having a diamond disk for conditioning the polishing pad and mounted to a second side of the housing, a second pulley coupled to the conditioning head for transferring the driving force from the drive pulley to the conditioning head, a timing belt engaged with the first and second pulleys, an air supply tube for supplying air under pressure to the conditoner head to force the head against a polishing pad of the CMP apparatus, and at least one sensor disposed in the housing for sensing the operation of the conditioning head.

Abstract: A presentation manager accepts standard commands or modified commands from legacy applications to provide text-based and graphic-based user interfaces. The presentation manager efficiently generates graphic-based displays for legacy applications by directly retrieving graphic definitions according to conventional host commands. The presentation manager provides standard host display protocol messaging for text-based clients (e.g., 3270 and 5250 terminals) and provides appropriate protocol messaging for other clients (e.g., graphical user interfaces and JAVA). Methods are provided for determining the protocol supported by a client.

Abstract: A method of fabricating a layered structure including a substrate, a first semiconductor layer with a first thermal expansion coefficient &agr;A, and a second semiconductor layer with a second thermal expansion coefficient &agr;B deposited on the first semiconductor layer, wherein &agr;Ais greater than &agr;B or smaller than &agr;B, includes: forming the first semiconductor layer, the second semiconductor layer, and a third semiconductor layer with a third thermal expansion coefficient &agr;C in this order on the substrate at a first temperature using a film deposition technique such as MOCVD, thereby forming a structural body including the substrate and the first to third semiconductor layers, wherein &agr;C is greater than &agr;B if &agr;A is greater than &agr;B or &agr;C is smaller than &agr;B if &agr;A is smaller than &agr;B; cooling the structural body to a second temperature, which is lower than the first temperature; and removing the third semiconductor layer from the structural body to expose the seco

Abstract: A start-up circuit includes a power supply node which receives a power supply voltage, a ground node which receives a ground voltage, a first node, a first capacitor which is coupled between the first node and the ground node, a supply circuit which is coupled between the power supply node and the first node, and which supplies an electrical charge from the power supply node to the first capacitor, a discharge circuit which is coupled between the first node and the ground node, and which discharges an electrical charge stored in the first capacitor to the ground node, and an output circuit which is connected to the first node, and which outputs a start-up signal when a voltage level of the first node becomes higher than a set voltage level.

Abstract: A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

Abstract: A method for manufacturing a semiconductor device employing a dielectric layer for forming a conductive layer into a three-dimensional shape. The dielectric layer is formed on a substrate in such a manner as to provide an intrinsic etch rate within the layer which increases in the direction of the thickness or depth of the dielectric layer. This variable intrinsic etch rate within the dielectric layer is achieved by changing one of a plurality of deposition variables. Once formed, the dielectric layer is selectively etched to form a through hole to contact a conductive area underlying the dielectric layer. A conductive layer is formed in the through hole, which may be a storage node of a capacitor.