Abstract: The invention relates to an alignment measuring method of a photolithography process by which a misalignment degree for each shot region of a wafer is indexed to improve the accuracy of determining the possibility of overlay defects. The method includes: measuring the overlay state of each pattern image transcribed to every shot region of a wafer; counting the number of shot regions judged as overlay defects with the misalignment amount of each measured shot region; calculating in percentage the number of shot regions judged as overlay defects against the number of total shot regions of the wafer; and comparing the calculated percentage value with a preset value to determine the possibility of rework.

Abstract: An active termination circuit is mounted in a memory circuit and includes a termination resistor which provides a termination resistance for the memory circuit, and a control circuit which receives an externally supplied active termination control signal, and which selectively switches on and off the termination resistor in response to the active termination control signal. The control circuit includes a synchronous input buffer and an asynchronous input buffer which each receive the active termination control signal, and a switching circuit which selectively outputs an output of said synchronous input buffer or an output of said asynchronous input buffer according to an operational mode of the memory circuit. The output of the switching circuit controls an on/off state of said termination resistor.

Abstract: A wafer cleaning device is disclosed in which a brush is integrally formed with a nozzle for supplying pure water, such that a uniform water screen is formed on a surface of a wafer and particles on the wafer can be entirely removed. The cleaning device includes injectors for ejecting pure water supplied from a pure water supplier onto a wafer; nozzles disposed at one end of each of the injectors; and a brush for cleaning the wafer while moving horizontally between a center and edges of the wafer. The injectors include a first injector for ejecting pure water at an upper position of the wafer toward the center of the wafer, and a second injector disposed adjacent to the brush along one side of a brush arm, the brush arm supporting the brush and moving the brush and second injector toward the wafer.

Abstract: An internal step-down power supply circuit improves response performance (transition from a standby state to an active state in particular) of a system, without increasing current consumption. The internal step-down power supply circuit includes an output node for outputting an internal step-down power-supply potential; a driver for adjusting an external power-supply potential VDD and supplying it to the output node; a divider circuit for dividing a voltage developed at the output node and outputting the divided voltage; and a differential amplifier for comparing the divided voltage and a reference voltage. The differential amplifier outputs a voltage equivalent to twice a predetermined gain. The operational amplifier sets the conductance of first transistors for feeding a current responsive to the reference voltage to twice or more the conductance of second transistors for feeding a current responsive to the divided voltage.

Abstract: A semiconductor device comprises a base semiconductor substrate (201) having an edge area (120) which surrounds an element forming area (110), a buried oxide film (202) provided over the base semiconductor substrate (201) in the element forming area (110), an element forming semiconductor substrate (203) provided over the buried oxide film (202).

Abstract: A shielding layer 23 is selectively formed on a single crystal silicon layer, an active area 25 is formed in the single crystal silicon layer by using the shielding layer 23 as a mask and an impurity layer 26 is formed at the edges at the sides of the active area 25 by using the shielding layer 23 as a mask and implanting an impurity diagonally from above. As a result, since an impurity layer can be formed by implanting ions of the impurity at the edges at the sides of the active area even when the size of the active area is reduced to the absolute limit, the occurrence of the parasitic transistor phenomenon or the edge transistor phenomenon along the edges at the sides of the active area can be prevented.

Abstract: A modular housing device includes a modular housing having a first side and a second side, at least one component disposed with said modular housing. The modular housing device further includes a bracket disposed on the second side.

Abstract: The period of time required for a parallel test can be shortened by widening the application range of the parallel test. In the semiconductor memory device having memory cell portions, there are provided a column controller that simultaneously activates a plurality of columns which are subject to degenerate substitution in a column redundant substitution; and a data read-out circuit that simultaneously reads out the data from a plurality of memory cells as selected by the above plurality of columns.

Abstract: A novel measurement method is provided capable of measuring characteristics of semiconductor integrated circuit devices without incurring the influence of external measuring means. A prescribed delay time applied to an address supplied from a microprocessor 11 to a memory 12 during normal operation is increased and a critical time where data corresponding to the address can no longer be read in by the microprocessor 11 from the memory 12 via the latch circuit 14 correctly is obtained. The delay time with which the address is supplied to the latch circuit 14 is increased with the address being supplied in a short-circuited manner to the latch circuit 14 rather than being supplied to the memory 12 and a short-circuit critical delay time where the address can no longer be read in correctly is obtained. A time difference corresponding to a difference in critical delay times is then obtained as the memory access time of the semiconductor integrated circuit device 10.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: A D/A converter is provided which is capable of avoiding an increase in occupied areas of the D/A converter on a board and of obtaining an output characteristic being excellent in linearity, which enables achievement of the D/A converter having a small integral-linearity error (INL) and a small differential-linearity error (DNL). The reference current composite blocks are cascaded between current controlling device groups and an output switch. At least one out of reference current composite blocks divides composite reference current amounts based on a predetermined weight and outputs them.

Abstract: A digital camera system has integrated accelerometers for determining static and dynamic accelerations of the digital camera system. Data relating to static and dynamic accelerations are stored with recorded image data for further processing, such as for correcting image data for roll, pitch and vibrations and for displaying recorded images with a predetermined orientation using information about, e.g., roll. Data may also be used on-the-fly for smear suppression caused by vibrations.

Abstract: An apparatus for and a method of heat-treating a wafer for use in producing a semiconductor device ensures a desired distribution of surface temperatures across the wafer. Spacers are used to space the wafer above a heat transfer plate. The spacers can be used to adjust the spacing and inclination of the wafer relative to the heat transfer plate by predetermined amounts determined in advance to produce the desired distribution of surface temperatures across the wafer during heat-treatment. With the present invention, wafers can be heat-treated during production using a plurality of bake units disposed in parallel because each of the bake units can be precisely adjusted using the spacers to produce surface temperature distributions similar to a standard surface temperature distribution. Accordingly, the productivity of the semiconductor manufacturing process can be markedly enhanced.

Abstract: A method of manufacturing a semiconductor device includes forming copper conductive patterns on an insulating layer formed on a semiconductor base, ashing the whole insulating layer including the copper conductive patterns at a temperature at which no oxide film is formed on the copper conductive patterns, and thereafter baking the whole insulating layer including the copper conductive patterns in an oxidative atmosphere at a temperature range of about 150° C. to about 200° C. After the baking step, an encapsulating resin is formed on the insulating layer including the copper conductive patterns.

Abstract: A content addressable memory includes a seek access circuit with four transistors connected in series between a pair of bit lines. The two inner transistors are driven by a data storage circuit; the outer two transistors function as enable transistors. A level shifting circuit receives an enable signal and shifts one or both of the logic levels of the enable signal so as to widen the potential difference between them. The shifted enable signal drives the enable transistors in the seek access circuit. Shifting the high logic level of the enable signal upward speeds up seek access by reducing the on-resistance of the enable transistors. Shifting the low logic level of the enable signal downward reduces subthreshold leakage through the seek access circuit, thereby reducing current consumption, speeding up read and write access, and preventing access errors.

Abstract: A plate assembly on which a wafer is supported in the processing chamber of a processing apparatus facilitates a precise transfer of the wafer therefrom even when a vacuum atmosphere is present in the chamber. The plate assembly includes an underlying support plate and a pad dedicated to support the rear surface of the wafer. A plurality of recesses, in the form of parallel grooves, extend in the upper surface of the pad so that the rear surface of the wafer can also be exposed to the vacuum atmosphere in the processing chamber. Accordingly, a pressure difference at both sides of the wafer is minimized. Thus, the wafer can be raised off of the plate assembly while the precise position thereof is maintained.

Abstract: A CMOSFET in which a p-type gate electrode and an n-type gate electrode are formed on a silicon substrate. The p-type gate electrode includes, in order, a p-type polycrystalline silicon layer and a tungsten silicide layer. The n-type gate electrode includes, in order, an n-type polycrystaline silicon layer and a tungsten silicide layer. A carbon-containing polycrystalline silicon layer, which is an impurity thermal diffusion prevention layer to suppress the interdiffusion of impurities, is provided between the p-type polycrystalline silicon layer and the tungsten silicide layer.

Abstract: A semiconductor integrated circuit having the function of the logical verification includes a plurality of units to be logically verified, which independently operate in the ordinary operation and include scan-path register respectively, which are operable as a shift register when connected in sequence in the logical verification operation; an instruction register scan input terminal to which an instruction for logical verification is externally inputted; an instruction register in which the instruction for logical verification is stored; an instruction decoder which decodes the instruction from the instruction register and executes the instruction for logical verification against said units; and a unit scan output terminal for externally outputting the processing result of the units. The circuit scale can be reduced by providing each unit with a scan-path register.

Abstract: A conditioning disk and a conditioner for a chemical mechanical polishing (CMP) pad, and a method of fabricating, reworking, and cleaning the conditioning disk, are utilized to improve conditioning efficiency, and to reduce production expenses. The conditioning disk for a CMP pad is divided into regions defined by a size difference of abrasive grains formed on the body surface in each region of the conditioning disk. The method of fabricating the conditioning disk is performed by forming adhesive films for attaching the abrasive grains onto the body surface multiple times. In addition, a used conditioning disk may be reworked by detaching the abrasive grains from the body, and attaching new abrasive grains. A used conditioning disk can also be cleaned of by-products of the conditioning process by a cleaning method using a HF solution or BOE (buffered oxide etch) solution.

Abstract: A semiconductor integrated circuit including a plurality of cores and/or a plurality of user defined logic (UDL) circuits, also includes a scan signal converting circuit to generate a plurality of scan signals to test the cores and/or the circuits adopting various scan styles in core-based design. The scan signal converting circuit converts scan signals corresponding one of the scan styles into various scan signals to control shift and normal operation of the embedded plural cores and/or the UDL circuits. As a result, the integrated circuit having a plurality of cores and/or the UDL circuits can be tested by the generated various scan signals from the scan signal converting circuit, under control of the scan signals corresponding to one of the scan styles. Therefore, the integrated circuit can easily perform test algorithms such as automatic test-pattern generation (ATPG) algorithm, and the like.