Patents Represented by Attorney Volentine Francos, PLLC
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Patent number: 6723215Abstract: A sputtering apparatus includes a sputtering chamber, a target disposed in the sputtering chamber, and a magnetic field generator for generating a rotating magnetic field at the front of the target. The magnetic field generator includes a main magnetic field-generating part that faces the back of the target and is horizontally (laterally) offset from a vertical line passing through the center of the target. A magnetic annulus of the main magnetic field-generating part forms a magnetic enclosure having openings therethrough at locations faced in the directions of the central and peripheral portions of the target. The magnetic field-generating part thus produces a magnetic field having a non-uniform distribution at the front of the target. A substrate is positioned within the sputtering chamber facing the front of the target. A metal layer is formed by sputtering atoms from the front of the target onto the substrate. The behavior of the sputtered atoms can be effectively controlled by the magnetic field.Type: GrantFiled: March 27, 2002Date of Patent: April 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kyou Park, Hyeon-Ill Um, Jai-Kwang Shin, Seong-Gu Kim
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Patent number: 6724052Abstract: A semiconductor device includes a substrate of a first conductive type, and a well region of an opposite second conductive type is formed in the substrate. A first impurity region of the first conductive type extends to a first depth within the well region, and a second impurity region of the first conductive type is spaced from the first impurity region to define a channel region therebetween and extends to a second depth within the well region. Preferably, the second depth is greater than the first depth. A gate electrode is located over the channel region, and a silicide layer is formed at a third depth within the first impurity region. The third depth is less than the first depth, and a difference between the first depth and the third depth is less than or equal to a difference at which a leakage current from the silicide layer to the well region is sufficient to electrically bias the well region through the silicide layer.Type: GrantFiled: July 15, 2002Date of Patent: April 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Sik Cho, Hoo-Seung Cho, Gyu-Chul Kim, Yong Park, Han-Soo Kim
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Patent number: 6724671Abstract: A nonvolatile semiconductor memory device and a method for testing the same by which the faulty memory device causing the unexpected data rewrite can be surely excluded. The test is carried out to judge whether or not a memory element storing a binary information corresponding to presence or not of an electric charge injected into a floating gate arranged on a semiconductor substrate so as to be electrically isolated therefrom, the semiconductor substrate including a source and a drain formed thereon, can exactly hold the electric charge injected to the floating gate in advance. In the test, an approximately equal voltage is applied to the source and drain as the voltage for drawing out the electric charge held in the floating gate.Type: GrantFiled: August 1, 2002Date of Patent: April 20, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Naotaka Yumoto
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Patent number: 6724474Abstract: Types of defects on a wafer are discriminated according to defect measurements obtained from a wafer inspection system which includes a plurality of dark field detectors. Using the wafer measurement system, it is determined whether first, second and third conditions are satisfied. The first condition is when a size of a defect on the wafer measured by the wafer inspection system is smaller than a limit value denoting a maximum size of crystal originated particles. The second condition is when a correlation between a plurality of defect light intensity values detected by a plurality of dark field detectors of the wafer measurement system satisfies a reference value. The third condition is when a location of the defect measured by the wafer inspection system is within a vacancy-rich area of the wafer. The type of the defect is then determined to be a crystal originated particle when the first, second and third conditions are all satisfied.Type: GrantFiled: September 28, 2000Date of Patent: April 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-yeol Heo, Kyoo-chul Cho, Kyong-rim Kang, Soo-yeul Choi
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Patent number: 6722885Abstract: A picture based psychological test, in particular a computer based implementation of the test and a system for automation of at least part of the test. The test may be used for the purpose of identifying a person's preferred way of interacting with other people. For example the test may be used to obtain knowledge of and describe relations within a family, a working team, a sports team, a study class, a political party, a religious community, etc, quickly, directly, and objectively. The test is non-verbal so that it is independent of the language used by the person whose relations and interactions are investigated.Type: GrantFiled: October 26, 2001Date of Patent: April 20, 2004Assignee: Westh Development ApSInventor: Finn Westh
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Patent number: 6723644Abstract: A method of manufacturing a semiconductor device is capable of preventing a dishing phenomenon from occurring without using dummy patterns. A plurality of conductive patterns are formed along the entire surface of a semiconductor substrate with an irregular pattern density. The conductive patterns have a first stopper layer at the top thereof. An interlayer insulating layer is formed on the conductive patterns. Next, a second stopper layer is formed on the interlayer insulating layer. An etching mask is formed on the second stopper layer so as to expose a first region having a conductive pattern density that is higher than that of another region(s). By using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region.Type: GrantFiled: March 12, 2002Date of Patent: April 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-yup Kim, Sang-rok Hah
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Patent number: 6723647Abstract: A method is disclosed for manufacturing a semiconductor device. Initially, a conductive layer is formed over a cell array region, in which high-integrated devices are formed, and over a non-cell region, which functions to assist a proper formation of the cell array region. An etching mask pattern is then formed over the conductive layer to form a conductive pattern over the cell array region and to remove the conductive layer formed on the non-cell region. The conductive pattern is actually formed by etching the conductive layer. An ion-assisted plasma etching is then implemented to form a pattern on the cell array region. This prevents the generation of arcing caused by independent conductive patterns formed on the non-cell region during the ion-assisted plasma etching.Type: GrantFiled: July 17, 2000Date of Patent: April 20, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Yun Kim, Yong-Hyeon Park
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Patent number: 6720645Abstract: In a semiconductor device, and a fabrication method thereof, a semiconductor element having bumps is mounted to a rear side of a base film. A plurality of inner leads are formed at a front side of the base film and located at peripheral portions of the semiconductor element. The inner leads are electrically connected with the bumps of the semiconductor element from the rear side of the base film. Apertures for connection of the bumps of the semiconductor element with the inner leads are provided at the base film. The apertures for connection are provided at locations which exclude locations of distal end portions of the inner leads. The distal end portions of the inner leads are fixed to the base film. The bumps of the semiconductor element and the base film are electrically connected through the apertures for connection from the rear surface.Type: GrantFiled: September 30, 2002Date of Patent: April 13, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Kazuaki Yoshiike, Shuichi Yamanaka
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Patent number: 6719808Abstract: A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate.Type: GrantFiled: October 25, 2000Date of Patent: April 13, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-soo Kim, Tae-hyuk Ahn, Won-seok Lee, Wan-jae Park
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Patent number: 6720835Abstract: A voltage-controlled oscillation (VCO) circuit includes a current generator, a variable capacitor having a capacitance value which changes in accordance with a tuning voltage, an inductor which is electrically connected to the variable capacitor in parallel, and a fixed, capacitor which is electrically connected to the variable capacitor in parallel. The variable capacitor is electrically connected to the current generator in series.Type: GrantFiled: August 6, 2002Date of Patent: April 13, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Ken Fujita
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Patent number: 6720833Abstract: The present invention provides a modulator which has a high degree of modulation and a good modulation sensitivity. The modulator comprises an oscillating circuit and a resonator portion, and this resonator portion comprises a reflective circuit board, a coupling line which is disposed on the reflective circuit board, a coupled load which is coupled to one end of the coupling line, a dielectric resonator which is disposed on the reflective circuit board and which is magnetically coupled with the coupling line, a window portion which is formed in the undersurface of the reflective circuit board directly beneath the coupling line, a waveguide resonator which is disposed on the undersurface of the reflective circuit board in the area that includes the window portion, and which is magnetically coupled with the coupling line, and a varactor diode which is inserted between the opposite signal conductor surfaces and of the waveguide resonator, and to which the input modulating signal terminal is connected.Type: GrantFiled: December 18, 2001Date of Patent: April 13, 2004Assignee: Oki Electric Industry Co., Ltd.Inventors: Bun Kobayashi, Masahiro Akiyama
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Patent number: 6720533Abstract: A heater assembly of a semiconductor device manufacturing apparatus minimizes a temperature difference between a peripheral portion and a central portion of the wafer being processed in the apparatus. The heater assembly includes a unitary resistive heating member in the form of a disc, heat blocks that divide the peripheral portion and central portion of the upper surface of the disc into respective heating sections, a support for supporting the heating member, and an electric power source for supplying electric current to the unitary heating member. The widths of the heating sections become greater towards the center of the heater, and thus the electrical resistance of the heater also increases in a direction towards the center of the heater. The power source for the heater includes a lead that extends from the bottom surface of the heater to a bottom portion of the heater support.Type: GrantFiled: August 13, 2002Date of Patent: April 13, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Gyeong-Su Keum, Hyung-Sik Hong, Chung-Hun Park, Eun-Seok Song, Jae-Han Park
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Patent number: 6720794Abstract: An output buffer circuit comprises an input terminal, an output terminal first and second inverters, a pull up control circuit, a pull down control circuit and first and second output transistors. Each of the first and second inverters is connected to the input terminal for outputting a signal having a slow rise up and fall down characteristic. Both of the pull up and pull down control circuits are connected to the input terminal and the output terminal. The pull up control circuit pulls up an output voltage of the first inverter when the output signal of the first inverter has a level lower than a first threshold voltage level. The pull up control circuit stops the pull up operation when the level of the output signal of the first inverter exceeds the first threshold voltage level. The pull down control circuit pulls down an output voltage of the second inverter when the output signal of the second inverter has a level higher than a second threshold voltage level.Type: GrantFiled: July 15, 2002Date of Patent: April 13, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Toshimichi Seike
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Patent number: 6717476Abstract: A modulator according to the invention includes: a PLL circuit that detects a phase difference between an input signal and a reference signal, an AGC circuit that controls a gain of a modulating signal and outputs a control signal, and a voltage controlled oscillation circuit that controls an oscillation frequency of a signal outputted from the PLL circuit on the basis of the control signal. Here, the voltage controlled oscillation circuit includes: a first voltage controlled reactance unit that inputs the signal outputted from the PLL circuit, a second voltage controlled reactance unit that inputs the control signal, and a high-frequency oscillation circuit connected in parallel with the first and second voltage controlled reactance units, which outputs the input signal. Thereby, the invention achieves to provide a modulator capable of compensating the deviation of the modulation factor, even when the frequency of the carrier signal varies.Type: GrantFiled: January 24, 2002Date of Patent: April 6, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Kazuo Suto
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Patent number: 6716668Abstract: A method for forming a semiconductor device includes providing a lead frame which has a die pad and a plurality of leads extending toward the outside of the die pad, mounting a semiconductor chip on the die pad, defining a plurality of inner leads by cutting a predetermined cut portion on each of the leads located around the semiconductor chip, and bonding a wire between the inner leads and the semiconductor chip. Accordingly, an applicable lead frame is provided for several sizes of a semiconductor chip.Type: GrantFiled: May 14, 2002Date of Patent: April 6, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Keiko Hayami
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Patent number: 6717252Abstract: A semiconductor device has a first chip fixed and connected to a substrate, wherein the first chip includes redistributions sealed with a sealing resin and for connecting between an integrated circuit formed on the surface of a semiconductor chip and ball pads, and solder bumps for connection to the substrate, which are respectively mounted on the ball pads.Type: GrantFiled: September 6, 2002Date of Patent: April 6, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Yoshihiro Saeki
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Patent number: 6717448Abstract: A data output method and data output circuit capable of increasing data output speed by reducing clock power while increasing sensing speed are provided. The data output method includes (a) precharging output terminals to a precharge voltage lower than a supply voltage; and (b) outputting differential output signals to the output terminals in response to differential input signals. In step (a) the output terminals are precharged in response to a clock signal having a first state, and in step (b) the differential signals are output to the output terminals in response to the clock signal having a second state. The voltage swing of the clock signal is set lower than the precharge voltage. The method further includes latching the differential output signals.Type: GrantFiled: August 6, 2002Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Nak-won Heo, Bai-sun Kong
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Patent number: 6716027Abstract: A semiconductor wafer boat has a plurality of discrete boat parts stacked one atop the other. Each of the of the boat parts includes a wafer support in the form of a plurality of columns each having a plurality of vertically spaced apart grooves for use in supporting semiconductor wafers as vertically spaced from one another. Corresponding ones of the grooves in the columns of a boat part can receive the outer peripheral edge of the wafer directly, or a ring plate to which the wafer is mounted. Each adjacent pair of boat parts has confronting end portions forming a joint at which the boat parts of the pair are freely coupled to one another such that each of the boat parts may be replaced independently of the other boat parts. Thus, when any of the boat parts experiences thermal deformation after long periods of use, the boat part may be readily replaced without damaging any part of the boat and without the costs associated with replacing the boat entirely.Type: GrantFiled: October 5, 2001Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Guen Kim, Bi-Cher Kim
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Patent number: 6717165Abstract: A technique is disclosed for detecting a turbo pump drive state in a tendetron accelerator that accelerates an ion beam to implant ions onto a semiconductor wafer. In particular the method of detecting a turbo pump driving state in the accelerator includes the steps of detecting a current applied to the turbo pump in the accelerator; converting the detected current to an optical signal to transmit it through an optical fiber; converting the optical signal transmitted through the optical fiber to an electric signal; displaying the current value of the converted electric signal; comparing the current value of the converted electric signal with a setting current value to generate an interlocking signal when the current value is out of a given range of the setting current value; and cutting off a power supply of the tendetron accelerator in accordance with the interlocking signal.Type: GrantFiled: September 27, 2001Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventor: Kwang-Ho Cha
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Patent number: 6716746Abstract: A semiconductor device includes a conductive region and line, and a contact plug electrically connecting the line and the region. The line is connected to the region via sidewalls of the plug, and the region is connected to the line via the bottom of the plug. The cross-sectional area of the plug decreases in a direction from an upper to lower portion thereof. In a first method of fabricating a semiconductor device having a self-aligned contact, the plug is formed after the line is formed in an interlayer dielectric layer. Portions of the dielectric layer and line are etched to form a contact hole in which the plug is formed. In a second method, a line having a gap therein is formed in an interlayer dielectric layer. Portions of the dielectric layer, including the gap in the line, are etched to form the contact hole.Type: GrantFiled: August 18, 2000Date of Patent: April 6, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: In Sung Kim, Joon Soo Park, Jung Hyeon Lee, Hyun Jae Kang