Abstract: The basic cell constituted by a semiconductor integrated circuit comprises two PMOS transistors and two NMOS transistors. By setting the gate widths of the gates of these transistors to prescribed lengths, the efficiency of use of elements within the basic cell is improved, and fine adjustment of the threshold voltage Vth and delay time Tpd becomes possible.

Abstract: A semiconductor memory device includes a redundancy circuit having predecode signal lines, a fuse predecode circuit, fuse decode circuit and an address decode circuit. The fuse predecode circuit is connected to the fuse predecode signal lines. The fuse predecode circuit includes drivers each of which generates a drive signal in response to one of first address signals received by the fuse predecode circuit. The fuse predecode circuit further includes terminal circuits connected to the predecode signal lines for latching signals appeared thereon, and fuse circuits each of which is connected between one of the predecode signal lines and a first potential source. Each of the fuse circuits includes a transistor having a control terminal connected to one of the drivers and a fuse connected to the transistor in series.

Abstract: An apparatus that automatically monitors speed and operating time of a semiconductor fabricating equipment lift that lifts a wafer cassette up/down. The apparatus automatically indicates operational state of the lift including lift speed time, use time after motor replacement and overhaul, and number of wafers processed, for confirmation by a worker.

Abstract: An ion implanting apparatus includes an analyzer unit for analyzing ions to be implanted into a wafer from among those ions in a beam produced by an ionization, a vacuum unit for producing a vacuum in the analyzer unit, a vacuum gauge for measuring the pressure inside the analyzer unit, and a shield for preventing a magnetic field employed by the analyzer unit from affecting the vacuum gauge. The shield has a plurality of magnetic field shielding plates encircling the vacuum gauge and dielectric material inserted between the magnetic shielding plates. The shield prevents the vacuum gauge from being influenced by the magnetic field generated by the analyzer unit. Therefore, the vacuum level inside the analyzer unit can be precisely measured.

Abstract: A wafer exposure apparatus includes a special wafer cooling unit, namely, an air showerhead, for controlling the temperature of a wafer which is to be transferred from a wafer pre-alignment system to a wafer stage of photolithography exposure equipment. The wafer which has been heated in the course of being transferred from a spin coater to the wafer pre-alignment system, and may be further heated by sensors of the wafer pre-alignment system, is cooled to the same temperature as that of a wafer stage. Accordingly, a thermal equilibrium may be rapidly established between the wafer and the wafer stage when the wafer is transferred to the wafer stage. Accordingly, excessive thermal expansion of the wafer caused by a difference in temperature between the wafer and the wafer stage is prevented. Therefore, an excessive error in aligning the wafer with the optics of the photolithography exposure equipment can be prevented.

Abstract: In a semiconductor device having memory cells and peripheral circuits, the memory cells and the peripheral circuits are formed on a semiconductor substrate. Source regions, drain regions and gate electrodes of MOS transistors in the peripheral circuits are comprised of a refractory metallic silicide layer. Gate electrodes of MOS transistors in the memory cells are comprised of the refractory metallic silicide. Source and drain regions of the MOS transistors in the memory cells are not comprised of the refractory metallic silicide layer.

Abstract: An end point detector for detecting the monitor light to control the operation of an etching process by the etching equipment based on changes in the monitor light supplied from plasma etching equipment. The end point detector includes a sensor body for detecting the monitor light and a collector barrel for guiding the monitor light from the etching equipment to the sensor body, wherein the collector barrel is detachable from the sensor body.

Abstract: A field-effect transistor is fabricated by depositing and patterning a layer of a semiconductor material and a first dielectric film to form a gate electrode covered by the remaining part of the first dielectric film, depositing a second dielectric film to form sidewalls on the gate electrode and first dielectric film, implanting a first impurity into the substrate to form source and drain regions, forming a third dielectric film masking at least the inner parts of the source and drain regions while exposing the first dielectric film, removing the first dielectric film by etching, and implanting a second impurity into the gate electrode. The first and second impurities may be, for example, boron difluoride and boron, respectively. The implantation parameters can be adjusted to form shallow source and drain regions and form a fully doped gate electrode.

Abstract: In a method of fabricating a semiconductor device, first metal interconnection patterns, first via patterns and second metal interconnection patterns are positioned in such a way that each of antenna ratios of the first metal patterns, the first via patterns and the second metal patterns becomes equal to or smaller than an allowable antenna ratio. Next, a width of each of the first metal patterns is broadened by a minimum line width of the first metal patterns. The broadened first metal patterns are connected at a first area where a distance between the broadened first metal patterns is smaller than a minimum size of the first via patterns. Then, a second area is extracted where the first metal patterns and the second metal patterns do not exist. Additional first via patterns are placed in the second area. Each of the additional first via patterns has a minimum size with a minimum pitch in the second area.

Abstract: A semiconductor wafer cleaning apparatus and method uses only one inner bath for chemical solution and de-ionized water cleaning, and includes a marangoni dryer for cleaning and drying semiconductor wafers. The apparatus includes a loading unit loaded with a cassette holding wafers; a moving mechanism for extracting the wafers from the cassette and moving the wafers into a loader; an inner bath for cleaning the wafers with a chemical solution or de-ionized water; a marangoni dryer including a hood, for moving the wafers from the loader into the bath, to be sealed to the bath; and a knife for supporting the wafers loaded into the bath at a lower portion thereof and moving the wafers up and down. Since the marangoni dryer is adhered to the bath during drying, the wafers are not affected by laminar flow or exhaustion and water marks do not occur thereon.

Abstract: In accordance with an exemplary embodiment of the present invention, an optical interleaver/deinterleaver includes a substrate having at least one window therein. The interleaver/deinterleaver further includes a first optical waveguide and a second optical fiber, which are disposed over a substrate. The first and second optical waveguides are coupled together at at least two locations to form optical couplers at each of the locations. The first optical waveguide has a first length between the two locations, and the second optical waveguide has a second length between the two locations wherein the first length is smaller than the second length. Illustratively, the first optical waveguide is disposed over the window, so that the window is along the first length of the first optical fiber.

Abstract: Protective tape is bonded onto a rear surface of a semiconductor element prior to a resin sealing step, and then only a primary surface of the semiconductor element is sealed with a resin layer. Cracks and warping which would otherwise be caused by an external force or foreign matter at an exposed rear surface of the semiconductor element are prevented. This facilitates a surface polishing step and also results in a lower profile for the semiconductor device, because the rear surface is not sealed with resin.

Abstract: A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first carrier gas flow rate while carrying a first impurity including boron flowing at a first impurity flow rate, (c) flowing a second carrier gas at a second carrier gas flow rate while carrying a second impurity including phosphorus flowing at a second impurity flow rate, and (d) flowing a silicon source material at a silicon source flow rate. The second carrier gas flow rate is greater than the first carrier gas flow rate.

Abstract: A semiconductor IC (Integrated Circuit) has blocks implemented as a standard cell each. Wirings are arranged in a wiring region for wiring the connections of circuit devices of a standard cell, which constitute utility circuit. A first and a second electrode each are formed in a particular polycrystalline silicon layer in the wiring region different from a layer assigned to the wirings. Either of the two electrodes is connected to a power supply while the other is connected to ground, forming a capacitance between the overlapping portions thereof.

Abstract: A first mask which is formed which exposes a cell array region and a peripheral circuit region of a semiconductor substrate. The cell array region and the peripheral circuit region are of a same conductive MOS type. Then, a preceding ion implantation process is implemented in both the cell array region and the peripheral circuit region utilizing the first mask. The preceding ion implantation process has ion implantation parameters corresponding to first implantation design specifications of one of the cell array region and the peripheral circuit region. Then, a second mask is formed which shields the one of the cell array region and the peripheral circuit region and which exposes the other of the cell array region and the peripheral circuit region. A subsequent ion implantation process is then implemented in the other of the cell array region and the peripheral circuit region utilizing the second mask.

Abstract: According to an exemplary embodiment of the present invention, an optical waveguide and method of use includes a grating which has a grating parameter that is adapted for dynamically variable non-uniform alteration. The non-uniform alteration of the grating parameter results in the introduction of a predetermined amount of chromatic dispersion and dispersion slope into an optical signal traversing the waveguide. According to another exemplary embodiment of the present invention, an optical apparatus and method of use includes a plurality of optical waveguides each of which have an optical grating and at least one of the waveguide gratings has a grating parameter that is adapted for dynamically variable non-uniform alteration. The optical apparatus further includes a device, which dynamically varies the grating parameters of each of the waveguides to selectively introduce chromatic dispersion and dispersion slope into an optical signal traversing the apparatus.

Abstract: An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1×1014 to 5×1015 cm−2. Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 &mgr;m or less.

Abstract: A semiconductor memory device and a method for manufacturing the same are provided.

Abstract: An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC11 to MCm1 connected with a word line WL1 to the read registers Rreg-1 to Rreg-m all at once, the data stored in the memory cells MC12 to MCm2 connected with a word line WL2 is transferred to the write registers Wreg-1 to Wreg-m all at once. The data stored in the read register is transmitted to an output means 123 through read data buses RD, /RD. The data stored in the write register is transmitted to the output means 123 through write data buses WD, /WD, an input/output means 122, and the second read data buses RD2, /RD2. The output means 123 compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD2, /RD2.