Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.

Abstract: A sales method includes accepting an order for goods from a customer, providing a code associated with the goods to the customer, and receiving the code from the customer prior to delivering the goods. A code verification method includes providing a code associated with goods ordered by a customer to the customer and receiving a verification request from a delivery agent tendering delivery of the goods to the customer. The verification request includes an asserted code provided by the customer. The method also includes determining whether the asserted code is the code previously provided to the customer. A repudiation resolution method includes receiving a request to reverse a credit charge for a purchase of goods from a customer and determining whether the customer provided a code associated with the goods to a delivery agent in response to the delivery agent tendering delivery of the goods to the customer.

Abstract: Architectural structure design methods, architectural structure design apparatuses, and articles of manufacture are described according to some aspects of the disclosure. In one aspect, an architectural structure design method includes responsive to user input, modifying a visual representation of an architectural structure, wherein the visual representation comprises an object of the architectural structure, first displaying the visual representation comprising the object at a first moment in time, wherein the object is positioned at a first location of a display screen, responsive to user input, selecting an attribute for the object from a second location of the display screen which is different than the first location of the display screen, responsive to user input, associating the attribute with the object after the selecting, and displaying the visual representation comprising the object having the attribute at a second moment in time after the associating.

Abstract: Cutting assemblies are disclosed that include an entrance portion and a receiving portion, with the receiving portion defining a receiving opening configured to be axially aligned with an entrance opening of the entrance portion when mounted to the surface of a cutting apparatus. Cutting assemblies are also provided that include a material carriage configured to be borne by a cutting apparatus. Cutting assemblies that include a material receiving portion configured to be slidably mounted to a surface of a cutting apparatus are also disclosed. Cutting methods are also disclosed that can include rotating a piece of material around the materials longitudinal axis and delivering the material to a cutting tool while the longitudinal axis of the material is aligned substantially opposite the direction of rotation of the cutting tool.

Abstract: A method of providing data to two client devices on a first network having a shared cache from a server device on a second network. An instance of substantially simultaneous requests for data being made to a server from two client devices on a same network is identified. In response to a first request for the data being received at a first point in time a first one of the two client devices is served with the requested data from the server such that the data is stored in the shared cache. The second one of the two client devices is directed to make a second request for the data at a second point in time, later than the first point in time, so that the requested data is available in the stored cache.

Abstract: Data storage devices include storage circuitry configured to store data; a first substantially planar card portion comprising the storage circuitry; an electrical interface electrically connected to the storage circuitry and located on one side of the first card portion; and one or more additional substantially planar card portions positioned below the other side of the first card portion and positioned parallel to one another and parallel to the first card portion. The combined thickness of the first card portion and the one or more additional card portions is sufficient to make contact with both an electrical interface of an electrical communications receptacle and a shell portion of the receptacle when the first card portion and the one or more additional card portions are inserted into the communications receptacle.

Abstract: Gas chromatography apparatuses are provided that can include a housing configured to substantially envelop the column within the compartment. Analytical instruments are provided that can include at least one chromatography column compartment having a volume of the less than 100 mL. Analytical methods are provided that can include increasing the temperature of a chromatography column at a rate of about 60° C./minute using less than about 40 W. Methods are also provided that include providing at least one gas chromatography column compartment configured to substantially envelop a gas chromatography column and performing analysis with the one compartment in the first operable position and/or transitioning portions to the second operable position to allow access to the one compartment.

Abstract: Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated.

Abstract: Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.

Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.

Abstract: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.

Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract: A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and forming a gate line extending through the line openings, over opposing sidewalls, and over a top of the fin. Source/drain regions are in the fin. Another method includes forming an interlayer dielectric over areas of the fin intended for source/drain regions, forming contact openings through the interlayer dielectric, and forming a source/drain plug in contact with an exposed portion of the spacer and in electrical connection with the top, one of opposing endwalls, and both of the opposing sidewalls of the fin.

Abstract: Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of features is photolithographically formed over the substrate. At least some of the features of said second set alternate with features of the first set. Spacer material is formed over and between the features of the first and second sets. The spacer material is anisotropically etched to form spacers along the features of the first and second sets. The features of the first and second sets are then removed to leave a pattern of the spacers over the substrate.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.

Abstract: Described herein is an electronic device provided with an electrode and a region of polymeric material set in contact with the electrode. The electrode has a polysilicon region and a silicide region, which coats the polysilicon region and is arranged, as interface, between the polysilicon region and the region of polymeric material. The polysilicon region is doped with a doping level that is a function of a desired work function at the interface with the region of polymeric material. The electronic device is, for example, a testing device for characterizing the properties of the polymeric material.

Abstract: Methods of defining ontologies, word disambiguation methods, computer systems, and articles of manufacture are described according to some aspects. In one aspect, a word disambiguation method includes accessing textual content to be disambiguated, wherein the textual content comprises a plurality of words individually comprising a plurality of word senses, for an individual word of the textual content, identifying one of the word senses of the word as indicative of the meaning of the word in the textual content, for the individual word, selecting one of a plurality of event classes of a lexical database ontology using the identified word sense of the individual word, and for the individual word, associating the selected one of the event classes with the textual content to provide disambiguation of a meaning of the individual word in the textual content.

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 ?, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.