Abstract: Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

Abstract: Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer.

Abstract: The present invention relates to devices for collecting and storing chemical samples and transferring those samples to analytical devices for analysis. In one implementation the device includes an interface for transferring samples and electrical signals. In another implementation, the device includes an analytical device having an interface for transferring samples and electrical signals with a sampling device. In another implementation, the device includes a sampling device having an interface for transferring samples and electrical signals with an analytical device.

Abstract: Provided is a burst scheduling method in an Optical Burst Switching (OBS) system in which a plurality of nodes are connected through a mesh-type network. When a TDB which has used many network resources via a plurality of nodes and an SHG burst generated in a previous node, among bursts including BCPs transmitted from the previous node, compete in a current node so as to occupy a specific output channel, scheduling is performed to cause the TDB to have a higher priority than the SHG burst such that the corresponding output channel is occupied. Therefore, it is possible to minimize a burst loss in a network node, thereby enhancing the overall system performance.

Abstract: Some embodiments include methods of utilizing block copolymer to form patterns between weirs. The methods may utilize liners along surfaces of the weirs to compensate for partial-width segments of the patterns in regions adjacent the weirs. Some embodiments include methods in which spaced apart structures are formed over a substrate, and outer surfaces of the structures are coated with a thickness of coating. Diblock copolymer is used to form a pattern across spaces between the structures. The diblock copolymer includes a pair of block constituents that have different affinities for the coating relative to one another. The pattern includes alternating segments, with the segments adjacent to the coating being shorter than the segments that are not adjacent to the coating. The coating thickness is about the amount by which the segments adjacent to the coating are shorter than the segments that are not adjacent to the coating.

Abstract: Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

Abstract: A roofing membrane retainer is provided having a cylindrical plate. The cylindrical plate has a central aperture for receiving a fastener. The plate also includes a pair of concentric inner and outer raised reinforcing ribs and a plurality of scoop-shaped projections. The scoop-shaped projections extend downwardly from the plate in concentric inner and outer cylindrical arrays. The inner cylindrical array of projections and the outer cylindrical array of projections are radially outward of the inner rib and the outer rib, respectively. The projections each comprise a scoop with a base periphery having an open mouth edge and a remaining peripheral portion contiguous with the plate. The projections in each array are spaced equidistance about the plate. The mouth edge of adjacent projections are oriented in alternating radial inward and outward directions.

Abstract: The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.

Abstract: Some embodiments include methods of forming metal-containing structures. A first metal-containing material may be formed over a substrate. After the first metal-containing material is formed, and while the substrate is within a reaction chamber, hydrogen-containing reactant may be used to form a hydrogen-containing layer over the first metal-containing material. The hydrogen-containing reactant may be, for example, formic acid and/or formaldehyde. Any unreacted hydrogen-containing reactant may be purged from within the reaction chamber, and then metal-containing precursor may be flowed into the reaction chamber. The hydrogen-containing layer may be used during conversion of the metal-containing precursor into a second metal-containing material that forms directly against the first metal-containing material. Some embodiments include methods of forming germanium-containing structures, such as, for example, methods of forming phase change materials containing germanium, antimony and tellurium.

Abstract: This invention generally pertains to a self-reversing tapping apparatus system, and more particularly, embodiments of this system include an improved coolant system, a reduction of the components which reverse rotational direction, and provides a modular tapping apparatus system.

Abstract: A method of forming a plurality of capacitors includes forming a plurality of individual capacitor electrodes using two masking steps. An earlier of the two masking steps is used to form an array of first openings over a plurality of storage node contacts. A later of the two masking steps is used to form an array of second openings received partially over and partially offset from the array of first openings. Overlapping portions of the first and second openings are received over the storage node contacts. After both of the two masking steps, conductive material of the individual capacitor electrodes is deposited into the overlapping portions of each of the first and second openings. The individual capacitor electrodes are incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.

Abstract: An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H2 is flowed to the substrate within the chamber. A second precursor gas is flowed to the first monolayer effective to react with the first monolayer and form a second monolayer on the substrate. The second monolayer comprises the metal. At least some of the flowing of the first metal halide-comprising precursor gas, at least some of the flowing of the H2, and at least some of the flowing of the second precursor gas are repeated effective to form a layer of material comprising the metal on the substrate.

Abstract: A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp2 bonds, and accelerating the clusters. A surface of a substrate is irradiated with the clusters. A material is formed on the surface using the carbon from the molecules. The material includes carbon and may optionally include hydrogen. The material may include graphene. The material may form a monolayer. The molecules may include one or more material selected from the group consisting of graphene, carbon allotropes, ethylene, and hydrocarbon molecules containing ethylenic moieties. A fused region may be formed in the substrate as an interface between the substrate and the material. The clusters may have diameters of at least 20 nanometers and may be accelerated to an energy of at least 0.5 keV.

Abstract: A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types. After activating the dopant, the substrate is bonded to the insulator material and at least some of the substrate is removed where bonded to the insulator material. After the removing, a memory cell is formed having a word line, an access diode, a state-changeable memory element containing chalcogenide phase change material, and a bit line all electrically connected in series, the access diode containing the junction as a p-n junction. A memory device includes an adhesion material over the insulator material and bonding the word line to the insulator material.

Abstract: An apparatus and method are provided for splicing together old and new thermoformable sheets in order to supply a continuous thermoforming operation. The method for joining together thermoformable sheets includes: providing a first thermoformable sheet with a trailing edge and a second thermoformable sheet with a leading edge; forming a terminal edge portion with a hot element along the trailing edge and a complementary terminal edge portion along the leading edge by severing a scrap sheet from each portion; laterally retracting each scrap portion away from the trailing edge and the leading edge; and joining together the first thermoformable sheet and the second thermoformable sheet by interlocking together the terminal edge portion with the complementary terminal edge portion.

Abstract: An intravascular port access device includes a first component having a chamber configured to attach reversibly to an intravenous line port. A second component reversibly attaches to the first component and contains a disinfecting agent and an applicator material. The second component is configured to be reversibly received over external surfaces of the intravenous line port. A method of cleansing an intravenous line port includes providing a port cleaning device having a first component includes a second cleaning agent. A third component has a microbiocidal agent and is reversibly attached to the first component. The second component is removed from the device, the external surfaces of the port are contacted with the second cleaning agent. the first cleaning agent is ejected from the chamber into the port, and the third component is used to cap the port.

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract: An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm.

Abstract: The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.