Abstract: The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions.

Abstract: Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The polysilazane may be converted to silicon nitride, silicon dioxide, or silicon oxynitride with thermal processing and exposure to an ambient that contains one or both of oxygen and nitrogen. The methods may include using the polysilazane in forming a charge trapping layer of a non-volatile memory cell. The methods may alternatively, or additionally include using the polysilazane in forming intergate dielectric material of a non-volatile memory cell. Some embodiments include methods of forming memory cells of a NAND memory array.

Abstract: A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are disclosed. In particular, the super deep implant is performed after spacer formation to significantly reduce junction capacitance in the channel region.

Abstract: A method is provided for selectively etching native oxides or other contaminants to metal nitrides and metal oxides during manufacture of a semiconductor device. The method utilizes a substantially non-aqueous etchant which includes a source of fluorine ions. In a preferred embodiment, the etchant comprises H2SO4 and HF. The etchant selectively etches native and doped oxides or other contaminants without excessively etching metal nitrides or metal oxides on the substrate or on adjacent exposed surfaces.

Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

Abstract: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.

Abstract: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.

Abstract: A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.

Abstract: Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a continuous concentration gradient of a second component relative to a first component. The continuous concentration gradient may correspond to a decreasing concentration of the second component as a distance from the first capacitor electrode increases. The first component may be selected from the group consisting of zirconium oxide, hafnium oxide and mixtures thereof; and the second component may be selected from the group consisting of niobium oxide, titanium oxide, strontium oxide and mixtures thereof. A second capacitor electrode may be formed over the first capacitor electrode. Some embodiments include capacitors that contain at least one metal oxide mixture having a continuous concentration gradient of the above-described second component relative to the above-described first component.

Abstract: A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an elevationally outermost silicon nitride-comprising surface. Such surface is treated with a fluid that is at least 99.5% H2O by volume. A polysilazane-comprising spin-on dielectric material is formed onto the H2O-treated silicon nitride-comprising surface. The polysilazane-comprising spin-on dielectric material is oxidized to form silicon oxide. Other implementations are contemplated.

Abstract: The present invention is a configurable trailer hitch that provides an extended towing position for transferring a tractor force to a load, and a retracted storage position for safely stowing the hitch under a towing vehicle. The trailer hitch has a spring loaded retaining pin which engages a hitch receiver when the trailer hitch is placed in the towing position, and a storage latch adapted to hold the hitch receiver when the trailer hitch is placed in the storage position.

Abstract: Energy systems, energy devices, energy utilization methods, and energy transfer methods are described. In one arrangement, energy utilization methods include providing first energy from a power grid to an induction generator at a first moment in time; using the induction generator and the first energy from the power grid, charging an energy storage device; using second energy from the energy storage device, powering a motor causing the induction generator to generate third energy during a second moment in time; and providing the third energy to the power grid. Other arrangements are described.

Abstract: Some embodiments include methods of forming memory cells. A semiconductor construction may be provided, with such construction including tunnel dielectric material over a semiconductor substrate. The construction may be placed within a chamber. While the construction is within the chamber, a plurality of charge-trapping centers may be dispersed over the tunnel dielectric material. The charge-trapping centers may be nanoclusters formed by sputter-depositing metallic nanoparticles into an aggregation chamber, and then aggregating groups of the nanoparticles into the nanoclusters. Also while the construction is within the chamber, electrically insulative material may be formed over and between the charge-trapping centers. Control gate material may then be formed over the electrically insulative material.

Abstract: A spectrometric analyzing device is capable of analyzing a thin film with high accuracy by using light having an arbitrary wavelength, such as not only infrared light but also visible light, ultraviolet light and X-ray, and using whatever refractive index of a supporting member of the thin film. A spectrometric analyzing device comprises a light source (1), a polarizing filter (2), a detection unit (3), a regression operation unit (4) and an absorbance spectrum calculation unit (5). The light source (1) emits light at n different angles of incidence (?n) to a measurement portion. The polarizing filter (2) shields an s-polarized component. The detection unit (3) detects transmitted spectra (S). The regression operation unit (4) uses the transmitted spectra (S) and a mixing ratio (R) to obtain an in-plane mode spectrum (sip) and an out-of-plane mode spectrum (sop) through a regression analysis.

Abstract: The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth elements incorporated within a dielectric material matrix. For instance, erbium or cerium can be within silicon nanocrystals dispersed throughout dielectric material of optical signal conduits. The dielectric material can define a path for the optical signal, and can be wrapped in a sheath which aids in keeping the optical signal along the path. The sheath can include any suitable barrier material, and can, for example, contain one or more metallic materials. The invention also includes methods of forming optical signal conduits, with some of such methods being methods in which the optical signal conduits are formed to be part of semiconductor constructions.

Abstract: The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: Some embodiments include methods of forming patterns in which a block copolymer-containing composition is formed over a substrate, and is then patterned to form a first mask. The block copolymer of the composition is subsequently induced into forming a repeating pattern within the first mask. Portions of the repeating pattern are then removed to form a second mask from the first mask. The patterning of the block copolymer-containing composition may utilize photolithography. Alternatively, the substrate may have regions which wet differently relative to one another with respect to the block copolymer-containing composition, and the patterning of the first mask may utilize such differences in wetting in forming the first mask.

Abstract: A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Abstract: A method and a system for classifying a plurality of random length boards of random grade, using a conveyer provided with reading units to read both the length and the grade of each board at a first end of said conveyer; a processor, receiving length and grade data from the reading units; calculating combinations of board lengths and grades and selecting a preferred combination of boards from the combinations; and a distribution section, located at a second end of the conveyer, and operated by the processor according to the preferred combination; the processor being fed with a large number of identified boards, from which to calculate the combinations of board lengths and grades, before they reach the distribution section.